Lantiq Synchronous Serial Controller (SSC) SPI master driver
|
|
Required properties:
|
- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
|
"intel,lgm-spi"
|
- #address-cells: see spi-bus.txt
|
- #size-cells: see spi-bus.txt
|
- reg: address and length of the spi master registers
|
- interrupts:
|
For compatible "intel,lgm-ssc" - the common interrupt number for
|
all of tx rx & err interrupts.
|
or
|
For rest of the compatibles, should contain the "spi_rx", "spi_tx" and
|
"spi_err" interrupt.
|
|
|
Optional properties:
|
- clocks: spi clock phandle
|
- num-cs: see spi-bus.txt, set to 8 if unset
|
- base-cs: the number of the first chip select, set to 1 if unset.
|
|
Example:
|
|
|
spi: spi@e100800 {
|
compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
|
reg = <0xE100800 0x100>;
|
interrupt-parent = <&icu0>;
|
interrupts = <22 23 24>;
|
interrupt-names = "spi_rx", "spi_tx", "spi_err";
|
#address-cells = <1>;
|
#size-cells = <1>;
|
num-cs = <6>;
|
base-cs = <1>;
|
};
|
|
ssc0: spi@e0800000 {
|
compatible = "intel,lgm-spi";
|
reg = <0xe0800000 0x400>;
|
interrupt-parent = <&ioapic1>;
|
interrupts = <35 1>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
clocks = <&cgu0 LGM_CLK_NGI>, <&cgu0 LGM_GCLK_SSC0>;
|
clock-names = "freq", "gate";
|
};
|
