Cadence Sierra PHY
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-----------------------
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Required properties:
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- compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
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Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
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- resets: Must contain an entry for each in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include "sierra_reset" and "sierra_apb".
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"sierra_reset" must control the reset line to the PHY.
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"sierra_apb" must control the reset line to the APB PHY
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interface ("sierra_apb" is optional).
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- reg: register range for the PHY.
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- #address-cells: Must be 1
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- #size-cells: Must be 0
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Optional properties:
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- clocks: Must contain an entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must contain "cmn_refclk_dig_div" and
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"cmn_refclk1_dig_div" for configuring the frequency of
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the clock to the lanes. "phy_clk" is deprecated.
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- cdns,autoconf: A boolean property whose presence indicates that the
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PHY registers will be configured by hardware. If not
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present, all sub-node optional properties must be
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provided.
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Sub-nodes:
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Each group of PHY lanes with a single master lane should be represented as
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a sub-node. Note that the actual configuration of each lane is determined by
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hardware strapping, and must match the configuration specified here.
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Sub-node required properties:
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- #phy-cells: Generic PHY binding; must be 0.
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- reg: The master lane number. This is the lowest numbered lane
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in the lane group.
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- resets: Must contain one entry which controls the reset line for the
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master lane of the sub-node.
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See ../reset/reset.txt for details.
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Sub-node optional properties:
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- cdns,num-lanes: Number of lanes in this group. From 1 to 4. The
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group is made up of consecutive lanes.
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- cdns,phy-type: Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
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configuration of lanes.
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Example:
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pcie_phy4: pcie-phy@fd240000 {
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compatible = "cdns,sierra-phy-t0";
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reg = <0x0 0xfd240000 0x0 0x40000>;
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resets = <&phyrst 0>, <&phyrst 1>;
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reset-names = "sierra_reset", "sierra_apb";
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clocks = <&phyclock>;
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clock-names = "phy_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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pcie0_phy0: pcie-phy@0 {
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reg = <0>;
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resets = <&phyrst 2>;
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cdns,num-lanes = <2>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_PCIE>;
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};
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pcie0_phy1: pcie-phy@2 {
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reg = <2>;
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resets = <&phyrst 4>;
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cdns,num-lanes = <1>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_PCIE>;
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};
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