NXP Layerscape PCIe Gen4 controller
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This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
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the common properties defined in mobiveil-pcie.txt.
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Required properties:
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- compatible: should contain the platform identifier such as:
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"fsl,lx2160a-pcie"
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- reg: base addresses and lengths of the PCIe controller register blocks.
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"csr_axi_slave": Bridge config registers
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"config_axi_slave": PCIe controller registers
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: It could include the following entries:
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"intr": The interrupt that is asserted for controller interrupts
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"aer": Asserted for aer interrupt when chip support the aer interrupt with
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none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
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"pme": Asserted for pme interrupt when chip support the pme interrupt with
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none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
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- dma-coherent: Indicates that the hardware IP block can ensure the coherency
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of the data transferred from/to the IP block. This can avoid the software
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cache flush/invalid actions, and improve the performance significantly.
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- msi-parent : See the generic MSI binding described in
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Documentation/devicetree/bindings/interrupt-controller/msi.txt.
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Example:
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pcie@3400000 {
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compatible = "fsl,lx2160a-pcie";
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reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
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0x80 0x00000000 0x0 0x00001000>; /* configuration space */
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reg-names = "csr_axi_slave", "config_axi_slave";
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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interrupt-names = "aer", "pme", "intr";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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apio-wins = <8>;
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ppio-wins = <8>;
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dma-coherent;
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bus-range = <0x0 0xff>;
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msi-parent = <&its>;
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ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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};
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