Marvell Orion SoC interrupt controllers
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* Main interrupt controller
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Required properties:
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- compatible: shall be "marvell,orion-intc"
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- reg: base address(es) of interrupt registers starting with CAUSE register
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
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The interrupt sources map to the corresponding bits in the interrupt
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registers, i.e.
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- 0 maps to bit 0 of first base address,
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- 1 maps to bit 1 of first base address,
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- 32 maps to bit 0 of second base address, and so on.
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Example:
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intc: interrupt-controller {
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compatible = "marvell,orion-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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/* Dove has 64 first level interrupts */
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reg = <0x20200 0x10>, <0x20210 0x10>;
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};
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* Bridge interrupt controller
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Required properties:
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- compatible: shall be "marvell,orion-bridge-intc"
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- reg: base address of bridge interrupt registers starting with CAUSE register
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- interrupts: bridge interrupt of the main interrupt controller
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
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Optional properties:
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- marvell,#interrupts: number of interrupts provided by bridge interrupt
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controller, defaults to 32 if not set
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Example:
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bridge_intc: interrupt-controller {
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compatible = "marvell,orion-bridge-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x20110 0x8>;
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interrupts = <0>;
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/* Dove bridge provides 5 interrupts */
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marvell,#interrupts = <5>;
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};
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