NXP Layerscape SoC qDMA Controller
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==================================
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This device follows the generic DMA bindings defined in dma/dma.txt.
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Required properties:
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- compatible: Must be one of
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"fsl,ls1021a-qdma": for LS1021A Board
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"fsl,ls1028a-qdma": for LS1028A Board
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"fsl,ls1043a-qdma": for ls1043A Board
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"fsl,ls1046a-qdma": for ls1046A Board
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- reg: Should contain the register's base address and length.
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- interrupts: Should contain a reference to the interrupt used by this
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device.
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- interrupt-names: Should contain interrupt names:
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"qdma-queue0": the block0 interrupt
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"qdma-queue1": the block1 interrupt
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"qdma-queue2": the block2 interrupt
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"qdma-queue3": the block3 interrupt
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"qdma-error": the error interrupt
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- fsl,dma-queues: Should contain number of queues supported.
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- dma-channels: Number of DMA channels supported
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- block-number: the virtual block number
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- block-offset: the offset of different virtual block
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- status-sizes: status queue size of per virtual block
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- queue-sizes: command queue size of per virtual block, the size number
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based on queues
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Optional properties:
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- dma-channels: Number of DMA channels supported by the controller.
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- big-endian: If present registers and hardware scatter/gather descriptors
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of the qDMA are implemented in big endian mode, otherwise in little
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mode.
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Examples:
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qdma: dma-controller@8390000 {
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compatible = "fsl,ls1021a-qdma";
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reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
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<0x0 0x8389000 0x0 0x1000>, /* Status regs */
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<0x0 0x838a000 0x0 0x2000>; /* Block regs */
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interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "qdma-error",
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"qdma-queue0", "qdma-queue1";
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dma-channels = <8>;
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block-number = <2>;
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block-offset = <0x1000>;
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fsl,dma-queues = <2>;
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status-sizes = <64>;
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queue-sizes = <64 64>;
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big-endian;
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};
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DMA clients must use the format described in dma/dma.txt file.
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