/*
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* Freescale i.MX6 PCI Express Root-Complex driver
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*
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* Copyright (C) 2013 Marek Vasut <marex@denx.de>
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*
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* Based on upstream Linux kernel driver:
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* pci-imx6.c: Sean Cross <xobs@kosagi.com>
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* pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include <errno.h>
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#include <asm/arch/sys_proto.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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#ifdef CONFIG_MX6SX
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#define MX6_DBI_ADDR 0x08ffc000
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#define MX6_IO_ADDR 0x08000000
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#define MX6_MEM_ADDR 0x08100000
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#define MX6_ROOT_ADDR 0x08f00000
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#else
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#define MX6_DBI_ADDR 0x01ffc000
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#define MX6_IO_ADDR 0x01000000
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#define MX6_MEM_ADDR 0x01100000
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#define MX6_ROOT_ADDR 0x01f00000
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#endif
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#define MX6_DBI_SIZE 0x4000
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#define MX6_IO_SIZE 0x100000
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#define MX6_MEM_SIZE 0xe00000
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#define MX6_ROOT_SIZE 0xfc000
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/* PCIe Port Logic registers (memory-mapped) */
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#define PL_OFFSET 0x700
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#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
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#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
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#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
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#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
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#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
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#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
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#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
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#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
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#define PCIE_PHY_CTRL_DATA_LOC 0
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#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
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#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
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#define PCIE_PHY_CTRL_WR_LOC 18
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#define PCIE_PHY_CTRL_RD_LOC 19
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#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
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#define PCIE_PHY_STAT_DATA_LOC 0
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#define PCIE_PHY_STAT_ACK_LOC 16
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/* PHY registers (not memory-mapped) */
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#define PCIE_PHY_RX_ASIC_OUT 0x100D
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#define PHY_RX_OVRD_IN_LO 0x1005
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#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
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#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
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#define PCIE_PHY_PUP_REQ (1 << 7)
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/* iATU registers */
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_CR1 0x904
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define PCIE_ATU_TYPE_IO (0x2 << 0)
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
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#define PCIE_ATU_CR2 0x908
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_LOWER_BASE 0x90C
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#define PCIE_ATU_UPPER_BASE 0x910
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#define PCIE_ATU_LIMIT 0x914
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#define PCIE_ATU_LOWER_TARGET 0x918
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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/*
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* PHY access functions
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*/
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static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
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{
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u32 val;
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u32 max_iterations = 10;
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u32 wait_counter = 0;
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do {
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val = readl(dbi_base + PCIE_PHY_STAT);
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val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
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wait_counter++;
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if (val == exp_val)
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return 0;
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udelay(1);
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} while (wait_counter < max_iterations);
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return -ETIMEDOUT;
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}
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static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
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{
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u32 val;
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int ret;
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val = addr << PCIE_PHY_CTRL_DATA_LOC;
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writel(val, dbi_base + PCIE_PHY_CTRL);
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val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
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writel(val, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 1);
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if (ret)
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return ret;
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val = addr << PCIE_PHY_CTRL_DATA_LOC;
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writel(val, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 0);
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if (ret)
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return ret;
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return 0;
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}
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/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
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static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
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{
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u32 val, phy_ctl;
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int ret;
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ret = pcie_phy_wait_ack(dbi_base, addr);
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if (ret)
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return ret;
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/* assert Read signal */
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phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
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writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 1);
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if (ret)
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return ret;
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val = readl(dbi_base + PCIE_PHY_STAT);
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*data = val & 0xffff;
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/* deassert Read signal */
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writel(0x00, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 0);
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if (ret)
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return ret;
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return 0;
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}
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static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
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{
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u32 var;
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int ret;
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/* write addr */
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/* cap addr */
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ret = pcie_phy_wait_ack(dbi_base, addr);
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if (ret)
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return ret;
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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writel(var, dbi_base + PCIE_PHY_CTRL);
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/* capture data */
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var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
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writel(var, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 1);
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if (ret)
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return ret;
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/* deassert cap data */
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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writel(var, dbi_base + PCIE_PHY_CTRL);
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/* wait for ack de-assertion */
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ret = pcie_phy_poll_ack(dbi_base, 0);
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if (ret)
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return ret;
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/* assert wr signal */
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var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
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writel(var, dbi_base + PCIE_PHY_CTRL);
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/* wait for ack */
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ret = pcie_phy_poll_ack(dbi_base, 1);
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if (ret)
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return ret;
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/* deassert wr signal */
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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writel(var, dbi_base + PCIE_PHY_CTRL);
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/* wait for ack de-assertion */
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ret = pcie_phy_poll_ack(dbi_base, 0);
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if (ret)
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return ret;
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writel(0x0, dbi_base + PCIE_PHY_CTRL);
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return 0;
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}
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static int imx6_pcie_link_up(void)
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{
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u32 rc, ltssm;
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int rx_valid, temp;
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/* link is debug bit 36, debug register 1 starts at bit 32 */
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rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1);
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if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
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!(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
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return -EAGAIN;
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/*
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* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
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* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
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* If (MAC/LTSSM.state == Recovery.RcvrLock)
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* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
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* to gen2 is stuck
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*/
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pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
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ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F;
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if (rx_valid & 0x01)
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return 0;
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if (ltssm != 0x0d)
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return 0;
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printf("transition to gen2 is stuck, reset PHY!\n");
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pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
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temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
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pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
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udelay(3000);
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pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
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temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
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pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
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return 0;
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}
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/*
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* iATU region setup
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*/
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static int imx_pcie_regions_setup(void)
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{
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/*
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* i.MX6 defines 16MB in the AXI address map for PCIe.
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*
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* That address space excepted the pcie registers is
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* split and defined into different regions by iATU,
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* with sizes and offsets as follows:
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*
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* 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
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* 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
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* 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
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*/
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/* CMD reg:I/O space, MEM space, and Bus Master Enable */
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setbits_le32(MX6_DBI_ADDR | PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
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setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION,
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PCI_CLASS_BRIDGE_PCI << 16);
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/* Region #0 is used for Outbound CFG space access. */
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writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
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writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE);
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writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE);
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writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT);
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writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
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writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET);
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writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
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writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2);
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return 0;
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}
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/*
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* PCI Express accessors
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*/
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static uint32_t get_bus_address(pci_dev_t d, int where)
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{
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uint32_t va_address;
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/* Reconfigure Region #0 */
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writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
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if (PCI_BUS(d) < 2)
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writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
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else
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writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1);
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if (PCI_BUS(d) == 0) {
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va_address = MX6_DBI_ADDR;
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} else {
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writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
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va_address = MX6_IO_ADDR + SZ_16M - SZ_1M;
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}
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va_address += (where & ~0x3);
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return va_address;
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}
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static int imx_pcie_addr_valid(pci_dev_t d)
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{
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if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
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return -EINVAL;
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if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
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return -EINVAL;
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return 0;
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}
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/*
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* Replace the original ARM DABT handler with a simple jump-back one.
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*
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* The problem here is that if we have a PCIe bridge attached to this PCIe
|
* controller, but no PCIe device is connected to the bridges' downstream
|
* port, the attempt to read/write from/to the config space will produce
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* a DABT. This is a behavior of the controller and can not be disabled
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* unfortuatelly.
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*
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* To work around the problem, we backup the current DABT handler address
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* and replace it with our own DABT handler, which only bounces right back
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* into the code.
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*/
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static void imx_pcie_fix_dabt_handler(bool set)
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{
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extern uint32_t *_data_abort;
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uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
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static const uint32_t data_abort_bounce_handler = 0xe25ef004;
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uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
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static uint32_t data_abort_backup;
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if (set) {
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data_abort_backup = *data_abort_addr;
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*data_abort_addr = data_abort_bounce_addr;
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} else {
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*data_abort_addr = data_abort_backup;
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}
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}
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static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
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int where, u32 *val)
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{
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uint32_t va_address;
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int ret;
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ret = imx_pcie_addr_valid(d);
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if (ret) {
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*val = 0xffffffff;
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return 0;
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}
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va_address = get_bus_address(d, where);
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/*
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* Read the PCIe config space. We must replace the DABT handler
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* here in case we got data abort from the PCIe controller, see
|
* imx_pcie_fix_dabt_handler() description. Note that writing the
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* "val" with valid value is also imperative here as in case we
|
* did got DABT, the val would contain random value.
|
*/
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imx_pcie_fix_dabt_handler(true);
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writel(0xffffffff, val);
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*val = readl(va_address);
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imx_pcie_fix_dabt_handler(false);
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return 0;
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}
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static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
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int where, u32 val)
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{
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uint32_t va_address = 0;
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int ret;
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ret = imx_pcie_addr_valid(d);
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if (ret)
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return ret;
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va_address = get_bus_address(d, where);
|
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/*
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* Write the PCIe config space. We must replace the DABT handler
|
* here in case we got data abort from the PCIe controller, see
|
* imx_pcie_fix_dabt_handler() description.
|
*/
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imx_pcie_fix_dabt_handler(true);
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writel(val, va_address);
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imx_pcie_fix_dabt_handler(false);
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return 0;
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}
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/*
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* Initial bus setup
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*/
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static int imx6_pcie_assert_core_reset(void)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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if (is_mx6dqp())
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setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
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#if defined(CONFIG_MX6SX)
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struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
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/* SSP_EN is not used on MX6SX anymore */
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setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
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/* Force PCIe PHY reset */
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setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
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/* Power up PCIe PHY */
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setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
|
#else
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/*
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* If the bootloader already enabled the link we need some special
|
* handling to get the core back into a state where it is safe to
|
* touch it for configuration. As there is no dedicated reset signal
|
* wired up for MX6QDL, we need to manually force LTSSM into "detect"
|
* state before completely disabling LTSSM, which is a prerequisite
|
* for core configuration.
|
*
|
* If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
|
* indication that the bootloader activated the link.
|
*/
|
if (is_mx6dq()) {
|
u32 val, gpr1, gpr12;
|
|
gpr1 = readl(&iomuxc_regs->gpr[1]);
|
gpr12 = readl(&iomuxc_regs->gpr[12]);
|
if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
|
(gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
|
val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR);
|
val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
|
val |= PCIE_PL_PFLR_FORCE_LINK;
|
|
imx_pcie_fix_dabt_handler(true);
|
writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR);
|
imx_pcie_fix_dabt_handler(false);
|
|
gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
|
writel(val, &iomuxc_regs->gpr[12]);
|
}
|
}
|
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
|
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
|
#endif
|
|
return 0;
|
}
|
|
static int imx6_pcie_init_phy(void)
|
{
|
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
|
|
clrsetbits_le32(&iomuxc_regs->gpr[12],
|
IOMUXC_GPR12_DEVICE_TYPE_MASK,
|
IOMUXC_GPR12_DEVICE_TYPE_RC);
|
clrsetbits_le32(&iomuxc_regs->gpr[12],
|
IOMUXC_GPR12_LOS_LEVEL_MASK,
|
IOMUXC_GPR12_LOS_LEVEL_9);
|
|
#ifdef CONFIG_MX6SX
|
clrsetbits_le32(&iomuxc_regs->gpr[12],
|
IOMUXC_GPR12_RX_EQ_MASK,
|
IOMUXC_GPR12_RX_EQ_2);
|
#endif
|
|
writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
|
(0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
|
(20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
|
(127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
|
(127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
|
&iomuxc_regs->gpr[8]);
|
|
return 0;
|
}
|
|
__weak int imx6_pcie_toggle_power(void)
|
{
|
#ifdef CONFIG_PCIE_IMX_POWER_GPIO
|
gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
|
mdelay(20);
|
gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
|
mdelay(20);
|
#endif
|
return 0;
|
}
|
|
__weak int imx6_pcie_toggle_reset(void)
|
{
|
/*
|
* See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
|
* for detailed understanding of the PCIe CR reset logic.
|
*
|
* The PCIe #PERST reset line _MUST_ be connected, otherwise your
|
* design does not conform to the specification. You must wait at
|
* least 20 ms after de-asserting the #PERST so the EP device can
|
* do self-initialisation.
|
*
|
* In case your #PERST pin is connected to a plain GPIO pin of the
|
* CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
|
* configuration file and the condition below will handle the rest
|
* of the reset toggling.
|
*
|
* In case your #PERST toggling logic is more complex, for example
|
* connected via CPLD or somesuch, you can override this function
|
* in your board file and implement reset logic as needed. You must
|
* not forget to wait at least 20 ms after de-asserting #PERST in
|
* this case either though.
|
*
|
* In case your #PERST line of the PCIe EP device is not connected
|
* at all, your design is broken and you should fix your design,
|
* otherwise you will observe problems like for example the link
|
* not coming up after rebooting the system back from running Linux
|
* that uses the PCIe as well OR the PCIe link might not come up in
|
* Linux at all in the first place since it's in some non-reset
|
* state due to being previously used in U-Boot.
|
*/
|
#ifdef CONFIG_PCIE_IMX_PERST_GPIO
|
gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
|
mdelay(20);
|
gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
|
mdelay(20);
|
#else
|
puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
|
#endif
|
return 0;
|
}
|
|
static int imx6_pcie_deassert_core_reset(void)
|
{
|
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
imx6_pcie_toggle_power();
|
|
enable_pcie_clock();
|
|
if (is_mx6dqp())
|
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
|
|
/*
|
* Wait for the clock to settle a bit, when the clock are sourced
|
* from the CPU, we need about 30 ms to settle.
|
*/
|
mdelay(50);
|
|
#if defined(CONFIG_MX6SX)
|
/* SSP_EN is not used on MX6SX anymore */
|
clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
|
/* Clear PCIe PHY reset bit */
|
clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
|
#else
|
/* Enable PCIe */
|
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
|
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
|
#endif
|
|
imx6_pcie_toggle_reset();
|
|
return 0;
|
}
|
|
static int imx_pcie_link_up(void)
|
{
|
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
uint32_t tmp;
|
int count = 0;
|
|
imx6_pcie_assert_core_reset();
|
imx6_pcie_init_phy();
|
imx6_pcie_deassert_core_reset();
|
|
imx_pcie_regions_setup();
|
|
/*
|
* FIXME: Force the PCIe RC to Gen1 operation
|
* The RC must be forced into Gen1 mode before bringing the link
|
* up, otherwise no downstream devices are detected. After the
|
* link is up, a managed Gen1->Gen2 transition can be initiated.
|
*/
|
tmp = readl(MX6_DBI_ADDR + 0x7c);
|
tmp &= ~0xf;
|
tmp |= 0x1;
|
writel(tmp, MX6_DBI_ADDR + 0x7c);
|
|
/* LTSSM enable, starting link. */
|
setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
|
|
while (!imx6_pcie_link_up()) {
|
udelay(10);
|
count++;
|
if (count >= 4000) {
|
#ifdef CONFIG_PCI_SCAN_SHOW
|
puts("PCI: pcie phy link never came up\n");
|
#endif
|
debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
|
readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
|
readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));
|
return -EINVAL;
|
}
|
}
|
|
return 0;
|
}
|
|
void imx_pcie_init(void)
|
{
|
/* Static instance of the controller. */
|
static struct pci_controller pcc;
|
struct pci_controller *hose = &pcc;
|
int ret;
|
|
memset(&pcc, 0, sizeof(pcc));
|
|
/* PCI I/O space */
|
pci_set_region(&hose->regions[0],
|
MX6_IO_ADDR, MX6_IO_ADDR,
|
MX6_IO_SIZE, PCI_REGION_IO);
|
|
/* PCI memory space */
|
pci_set_region(&hose->regions[1],
|
MX6_MEM_ADDR, MX6_MEM_ADDR,
|
MX6_MEM_SIZE, PCI_REGION_MEM);
|
|
/* System memory space */
|
pci_set_region(&hose->regions[2],
|
MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
|
0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
|
hose->region_count = 3;
|
|
pci_set_ops(hose,
|
pci_hose_read_config_byte_via_dword,
|
pci_hose_read_config_word_via_dword,
|
imx_pcie_read_config,
|
pci_hose_write_config_byte_via_dword,
|
pci_hose_write_config_word_via_dword,
|
imx_pcie_write_config);
|
|
/* Start the controller. */
|
ret = imx_pcie_link_up();
|
|
if (!ret) {
|
pci_register_hose(hose);
|
hose->last_busno = pci_hose_scan(hose);
|
}
|
}
|
|
void imx_pcie_remove(void)
|
{
|
imx6_pcie_assert_core_reset();
|
}
|
|
/* Probe function. */
|
void pci_init_board(void)
|
{
|
imx_pcie_init();
|
}
|
