/*
|
* wanXL serial card driver for Linux
|
* host part
|
*
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* Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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* Status:
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* - Only DTE (external clock) support with NRZ and NRZI encodings
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* - wanXL100 will require minor driver modifications, no access to hw
|
*/
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|
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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|
#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/fcntl.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/netdevice.h>
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#include <linux/hdlc.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include "wanxl.h"
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static const char* version = "wanXL serial card driver version: 0.48";
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#define PLX_CTL_RESET 0x40000000 /* adapter reset */
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#undef DEBUG_PKT
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#undef DEBUG_PCI
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/* MAILBOX #1 - PUTS COMMANDS */
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#define MBX1_CMD_ABORTJ 0x85000000 /* Abort and Jump */
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#ifdef __LITTLE_ENDIAN
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#define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */
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#else
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#define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */
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#endif
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/* MAILBOX #2 - DRAM SIZE */
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#define MBX2_MEMSZ_MASK 0xFFFF0000 /* PUTS Memory Size Register mask */
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|
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struct port {
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struct net_device *dev;
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struct card *card;
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spinlock_t lock; /* for wanxl_xmit */
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int node; /* physical port #0 - 3 */
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unsigned int clock_type;
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int tx_in, tx_out;
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struct sk_buff *tx_skbs[TX_BUFFERS];
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};
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|
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struct card_status {
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desc_t rx_descs[RX_QUEUE_LENGTH];
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port_status_t port_status[4];
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};
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|
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struct card {
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int n_ports; /* 1, 2 or 4 ports */
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u8 irq;
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u8 __iomem *plx; /* PLX PCI9060 virtual base address */
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struct pci_dev *pdev; /* for pci_name(pdev) */
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int rx_in;
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struct sk_buff *rx_skbs[RX_QUEUE_LENGTH];
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struct card_status *status; /* shared between host and card */
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dma_addr_t status_address;
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struct port ports[0]; /* 1 - 4 port structures follow */
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};
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|
|
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static inline struct port *dev_to_port(struct net_device *dev)
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{
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return (struct port *)dev_to_hdlc(dev)->priv;
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}
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static inline port_status_t *get_status(struct port *port)
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{
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return &port->card->status->port_status[port->node];
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}
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#ifdef DEBUG_PCI
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static inline dma_addr_t pci_map_single_debug(struct pci_dev *pdev, void *ptr,
|
size_t size, int direction)
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{
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dma_addr_t addr = pci_map_single(pdev, ptr, size, direction);
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if (addr + size > 0x100000000LL)
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pr_crit("%s: pci_map_single() returned memory at 0x%llx!\n",
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pci_name(pdev), (unsigned long long)addr);
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return addr;
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}
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#undef pci_map_single
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#define pci_map_single pci_map_single_debug
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#endif
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|
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/* Cable and/or personality module change interrupt service */
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static inline void wanxl_cable_intr(struct port *port)
|
{
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u32 value = get_status(port)->cable;
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int valid = 1;
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const char *cable, *pm, *dte = "", *dsr = "", *dcd = "";
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switch(value & 0x7) {
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case STATUS_CABLE_V35: cable = "V.35"; break;
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case STATUS_CABLE_X21: cable = "X.21"; break;
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case STATUS_CABLE_V24: cable = "V.24"; break;
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case STATUS_CABLE_EIA530: cable = "EIA530"; break;
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case STATUS_CABLE_NONE: cable = "no"; break;
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default: cable = "invalid";
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}
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switch((value >> STATUS_CABLE_PM_SHIFT) & 0x7) {
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case STATUS_CABLE_V35: pm = "V.35"; break;
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case STATUS_CABLE_X21: pm = "X.21"; break;
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case STATUS_CABLE_V24: pm = "V.24"; break;
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case STATUS_CABLE_EIA530: pm = "EIA530"; break;
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case STATUS_CABLE_NONE: pm = "no personality"; valid = 0; break;
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default: pm = "invalid personality"; valid = 0;
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}
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if (valid) {
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if ((value & 7) == ((value >> STATUS_CABLE_PM_SHIFT) & 7)) {
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dsr = (value & STATUS_CABLE_DSR) ? ", DSR ON" :
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", DSR off";
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dcd = (value & STATUS_CABLE_DCD) ? ", carrier ON" :
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", carrier off";
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}
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dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE";
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}
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netdev_info(port->dev, "%s%s module, %s cable%s%s\n",
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pm, dte, cable, dsr, dcd);
|
|
if (value & STATUS_CABLE_DCD)
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netif_carrier_on(port->dev);
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else
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netif_carrier_off(port->dev);
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}
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|
|
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/* Transmit complete interrupt service */
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static inline void wanxl_tx_intr(struct port *port)
|
{
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struct net_device *dev = port->dev;
|
while (1) {
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desc_t *desc = &get_status(port)->tx_descs[port->tx_in];
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struct sk_buff *skb = port->tx_skbs[port->tx_in];
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|
switch (desc->stat) {
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case PACKET_FULL:
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case PACKET_EMPTY:
|
netif_wake_queue(dev);
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return;
|
|
case PACKET_UNDERRUN:
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dev->stats.tx_errors++;
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dev->stats.tx_fifo_errors++;
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break;
|
|
default:
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dev->stats.tx_packets++;
|
dev->stats.tx_bytes += skb->len;
|
}
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desc->stat = PACKET_EMPTY; /* Free descriptor */
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pci_unmap_single(port->card->pdev, desc->address, skb->len,
|
PCI_DMA_TODEVICE);
|
dev_kfree_skb_irq(skb);
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port->tx_in = (port->tx_in + 1) % TX_BUFFERS;
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}
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}
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|
|
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/* Receive complete interrupt service */
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static inline void wanxl_rx_intr(struct card *card)
|
{
|
desc_t *desc;
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while (desc = &card->status->rx_descs[card->rx_in],
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desc->stat != PACKET_EMPTY) {
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if ((desc->stat & PACKET_PORT_MASK) > card->n_ports)
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pr_crit("%s: received packet for nonexistent port\n",
|
pci_name(card->pdev));
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else {
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struct sk_buff *skb = card->rx_skbs[card->rx_in];
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struct port *port = &card->ports[desc->stat &
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PACKET_PORT_MASK];
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struct net_device *dev = port->dev;
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if (!skb)
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dev->stats.rx_dropped++;
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else {
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pci_unmap_single(card->pdev, desc->address,
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BUFFER_LENGTH,
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PCI_DMA_FROMDEVICE);
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skb_put(skb, desc->length);
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#ifdef DEBUG_PKT
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printk(KERN_DEBUG "%s RX(%i):", dev->name,
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skb->len);
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debug_frame(skb);
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#endif
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dev->stats.rx_packets++;
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dev->stats.rx_bytes += skb->len;
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skb->protocol = hdlc_type_trans(skb, dev);
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netif_rx(skb);
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skb = NULL;
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}
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if (!skb) {
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skb = dev_alloc_skb(BUFFER_LENGTH);
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desc->address = skb ?
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pci_map_single(card->pdev, skb->data,
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BUFFER_LENGTH,
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PCI_DMA_FROMDEVICE) : 0;
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card->rx_skbs[card->rx_in] = skb;
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}
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}
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desc->stat = PACKET_EMPTY; /* Free descriptor */
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card->rx_in = (card->rx_in + 1) % RX_QUEUE_LENGTH;
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}
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}
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static irqreturn_t wanxl_intr(int irq, void* dev_id)
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{
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struct card *card = dev_id;
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int i;
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u32 stat;
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int handled = 0;
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|
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while((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {
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handled = 1;
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writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);
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for (i = 0; i < card->n_ports; i++) {
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if (stat & (1 << (DOORBELL_FROM_CARD_TX_0 + i)))
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wanxl_tx_intr(&card->ports[i]);
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if (stat & (1 << (DOORBELL_FROM_CARD_CABLE_0 + i)))
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wanxl_cable_intr(&card->ports[i]);
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}
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if (stat & (1 << DOORBELL_FROM_CARD_RX))
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wanxl_rx_intr(card);
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}
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return IRQ_RETVAL(handled);
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}
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static netdev_tx_t wanxl_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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struct port *port = dev_to_port(dev);
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desc_t *desc;
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spin_lock(&port->lock);
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desc = &get_status(port)->tx_descs[port->tx_out];
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if (desc->stat != PACKET_EMPTY) {
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/* should never happen - previous xmit should stop queue */
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#ifdef DEBUG_PKT
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printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
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#endif
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netif_stop_queue(dev);
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spin_unlock(&port->lock);
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return NETDEV_TX_BUSY; /* request packet to be queued */
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}
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#ifdef DEBUG_PKT
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printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
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debug_frame(skb);
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#endif
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port->tx_skbs[port->tx_out] = skb;
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desc->address = pci_map_single(port->card->pdev, skb->data, skb->len,
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PCI_DMA_TODEVICE);
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desc->length = skb->len;
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desc->stat = PACKET_FULL;
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writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node),
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port->card->plx + PLX_DOORBELL_TO_CARD);
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port->tx_out = (port->tx_out + 1) % TX_BUFFERS;
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if (get_status(port)->tx_descs[port->tx_out].stat != PACKET_EMPTY) {
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netif_stop_queue(dev);
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#ifdef DEBUG_PKT
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printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
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#endif
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}
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spin_unlock(&port->lock);
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return NETDEV_TX_OK;
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}
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static int wanxl_attach(struct net_device *dev, unsigned short encoding,
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unsigned short parity)
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{
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struct port *port = dev_to_port(dev);
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if (encoding != ENCODING_NRZ &&
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encoding != ENCODING_NRZI)
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return -EINVAL;
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if (parity != PARITY_NONE &&
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parity != PARITY_CRC32_PR1_CCITT &&
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parity != PARITY_CRC16_PR1_CCITT &&
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parity != PARITY_CRC32_PR0_CCITT &&
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parity != PARITY_CRC16_PR0_CCITT)
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return -EINVAL;
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get_status(port)->encoding = encoding;
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get_status(port)->parity = parity;
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return 0;
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}
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static int wanxl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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{
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const size_t size = sizeof(sync_serial_settings);
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sync_serial_settings line;
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struct port *port = dev_to_port(dev);
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if (cmd != SIOCWANDEV)
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return hdlc_ioctl(dev, ifr, cmd);
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switch (ifr->ifr_settings.type) {
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case IF_GET_IFACE:
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ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
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if (ifr->ifr_settings.size < size) {
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ifr->ifr_settings.size = size; /* data size wanted */
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return -ENOBUFS;
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}
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memset(&line, 0, sizeof(line));
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line.clock_type = get_status(port)->clocking;
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line.clock_rate = 0;
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line.loopback = 0;
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if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size))
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return -EFAULT;
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return 0;
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case IF_IFACE_SYNC_SERIAL:
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if (!capable(CAP_NET_ADMIN))
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return -EPERM;
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if (dev->flags & IFF_UP)
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return -EBUSY;
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if (copy_from_user(&line, ifr->ifr_settings.ifs_ifsu.sync,
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size))
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return -EFAULT;
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if (line.clock_type != CLOCK_EXT &&
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line.clock_type != CLOCK_TXFROMRX)
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return -EINVAL; /* No such clock setting */
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if (line.loopback != 0)
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return -EINVAL;
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get_status(port)->clocking = line.clock_type;
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return 0;
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default:
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return hdlc_ioctl(dev, ifr, cmd);
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}
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}
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static int wanxl_open(struct net_device *dev)
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{
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struct port *port = dev_to_port(dev);
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u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
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unsigned long timeout;
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int i;
|
|
if (get_status(port)->open) {
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netdev_err(dev, "port already open\n");
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return -EIO;
|
}
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if ((i = hdlc_open(dev)) != 0)
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return i;
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port->tx_in = port->tx_out = 0;
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for (i = 0; i < TX_BUFFERS; i++)
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get_status(port)->tx_descs[i].stat = PACKET_EMPTY;
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/* signal the card */
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writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr);
|
|
timeout = jiffies + HZ;
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do {
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if (get_status(port)->open) {
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netif_start_queue(dev);
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return 0;
|
}
|
} while (time_after(timeout, jiffies));
|
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netdev_err(dev, "unable to open port\n");
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/* ask the card to close the port, should it be still alive */
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writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr);
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return -EFAULT;
|
}
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|
|
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static int wanxl_close(struct net_device *dev)
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{
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struct port *port = dev_to_port(dev);
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unsigned long timeout;
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int i;
|
|
hdlc_close(dev);
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/* signal the card */
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writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node),
|
port->card->plx + PLX_DOORBELL_TO_CARD);
|
|
timeout = jiffies + HZ;
|
do {
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if (!get_status(port)->open)
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break;
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} while (time_after(timeout, jiffies));
|
|
if (get_status(port)->open)
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netdev_err(dev, "unable to close port\n");
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netif_stop_queue(dev);
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for (i = 0; i < TX_BUFFERS; i++) {
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desc_t *desc = &get_status(port)->tx_descs[i];
|
|
if (desc->stat != PACKET_EMPTY) {
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desc->stat = PACKET_EMPTY;
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pci_unmap_single(port->card->pdev, desc->address,
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port->tx_skbs[i]->len,
|
PCI_DMA_TODEVICE);
|
dev_kfree_skb(port->tx_skbs[i]);
|
}
|
}
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return 0;
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}
|
|
|
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static struct net_device_stats *wanxl_get_stats(struct net_device *dev)
|
{
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struct port *port = dev_to_port(dev);
|
|
dev->stats.rx_over_errors = get_status(port)->rx_overruns;
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dev->stats.rx_frame_errors = get_status(port)->rx_frame_errors;
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dev->stats.rx_errors = dev->stats.rx_over_errors +
|
dev->stats.rx_frame_errors;
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return &dev->stats;
|
}
|
|
|
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static int wanxl_puts_command(struct card *card, u32 cmd)
|
{
|
unsigned long timeout = jiffies + 5 * HZ;
|
|
writel(cmd, card->plx + PLX_MAILBOX_1);
|
do {
|
if (readl(card->plx + PLX_MAILBOX_1) == 0)
|
return 0;
|
|
schedule();
|
}while (time_after(timeout, jiffies));
|
|
return -1;
|
}
|
|
|
|
static void wanxl_reset(struct card *card)
|
{
|
u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;
|
|
writel(0x80, card->plx + PLX_MAILBOX_0);
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writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);
|
readl(card->plx + PLX_CONTROL); /* wait for posted write */
|
udelay(1);
|
writel(old_value, card->plx + PLX_CONTROL);
|
readl(card->plx + PLX_CONTROL); /* wait for posted write */
|
}
|
|
|
|
static void wanxl_pci_remove_one(struct pci_dev *pdev)
|
{
|
struct card *card = pci_get_drvdata(pdev);
|
int i;
|
|
for (i = 0; i < card->n_ports; i++) {
|
unregister_hdlc_device(card->ports[i].dev);
|
free_netdev(card->ports[i].dev);
|
}
|
|
/* unregister and free all host resources */
|
if (card->irq)
|
free_irq(card->irq, card);
|
|
wanxl_reset(card);
|
|
for (i = 0; i < RX_QUEUE_LENGTH; i++)
|
if (card->rx_skbs[i]) {
|
pci_unmap_single(card->pdev,
|
card->status->rx_descs[i].address,
|
BUFFER_LENGTH, PCI_DMA_FROMDEVICE);
|
dev_kfree_skb(card->rx_skbs[i]);
|
}
|
|
if (card->plx)
|
iounmap(card->plx);
|
|
if (card->status)
|
pci_free_consistent(pdev, sizeof(struct card_status),
|
card->status, card->status_address);
|
|
pci_release_regions(pdev);
|
pci_disable_device(pdev);
|
kfree(card);
|
}
|
|
|
#include "wanxlfw.inc"
|
|
static const struct net_device_ops wanxl_ops = {
|
.ndo_open = wanxl_open,
|
.ndo_stop = wanxl_close,
|
.ndo_start_xmit = hdlc_start_xmit,
|
.ndo_do_ioctl = wanxl_ioctl,
|
.ndo_get_stats = wanxl_get_stats,
|
};
|
|
static int wanxl_pci_init_one(struct pci_dev *pdev,
|
const struct pci_device_id *ent)
|
{
|
struct card *card;
|
u32 ramsize, stat;
|
unsigned long timeout;
|
u32 plx_phy; /* PLX PCI base address */
|
u32 mem_phy; /* memory PCI base addr */
|
u8 __iomem *mem; /* memory virtual base addr */
|
int i, ports, alloc_size;
|
|
#ifndef MODULE
|
pr_info_once("%s\n", version);
|
#endif
|
|
i = pci_enable_device(pdev);
|
if (i)
|
return i;
|
|
/* QUICC can only access first 256 MB of host RAM directly,
|
but PLX9060 DMA does 32-bits for actual packet data transfers */
|
|
/* FIXME when PCI/DMA subsystems are fixed.
|
We set both dma_mask and consistent_dma_mask to 28 bits
|
and pray pci_alloc_consistent() will use this info. It should
|
work on most platforms */
|
if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(28)) ||
|
pci_set_dma_mask(pdev, DMA_BIT_MASK(28))) {
|
pr_err("No usable DMA configuration\n");
|
pci_disable_device(pdev);
|
return -EIO;
|
}
|
|
i = pci_request_regions(pdev, "wanXL");
|
if (i) {
|
pci_disable_device(pdev);
|
return i;
|
}
|
|
switch (pdev->device) {
|
case PCI_DEVICE_ID_SBE_WANXL100: ports = 1; break;
|
case PCI_DEVICE_ID_SBE_WANXL200: ports = 2; break;
|
default: ports = 4;
|
}
|
|
alloc_size = sizeof(struct card) + ports * sizeof(struct port);
|
card = kzalloc(alloc_size, GFP_KERNEL);
|
if (card == NULL) {
|
pci_release_regions(pdev);
|
pci_disable_device(pdev);
|
return -ENOBUFS;
|
}
|
|
pci_set_drvdata(pdev, card);
|
card->pdev = pdev;
|
|
card->status = pci_alloc_consistent(pdev,
|
sizeof(struct card_status),
|
&card->status_address);
|
if (card->status == NULL) {
|
wanxl_pci_remove_one(pdev);
|
return -ENOBUFS;
|
}
|
|
#ifdef DEBUG_PCI
|
printk(KERN_DEBUG "wanXL %s: pci_alloc_consistent() returned memory"
|
" at 0x%LX\n", pci_name(pdev),
|
(unsigned long long)card->status_address);
|
#endif
|
|
/* FIXME when PCI/DMA subsystems are fixed.
|
We set both dma_mask and consistent_dma_mask back to 32 bits
|
to indicate the card can do 32-bit DMA addressing */
|
if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) ||
|
pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
|
pr_err("No usable DMA configuration\n");
|
wanxl_pci_remove_one(pdev);
|
return -EIO;
|
}
|
|
/* set up PLX mapping */
|
plx_phy = pci_resource_start(pdev, 0);
|
|
card->plx = ioremap_nocache(plx_phy, 0x70);
|
if (!card->plx) {
|
pr_err("ioremap() failed\n");
|
wanxl_pci_remove_one(pdev);
|
return -EFAULT;
|
}
|
|
#if RESET_WHILE_LOADING
|
wanxl_reset(card);
|
#endif
|
|
timeout = jiffies + 20 * HZ;
|
while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {
|
if (time_before(timeout, jiffies)) {
|
pr_warn("%s: timeout waiting for PUTS to complete\n",
|
pci_name(pdev));
|
wanxl_pci_remove_one(pdev);
|
return -ENODEV;
|
}
|
|
switch(stat & 0xC0) {
|
case 0x00: /* hmm - PUTS completed with non-zero code? */
|
case 0x80: /* PUTS still testing the hardware */
|
break;
|
|
default:
|
pr_warn("%s: PUTS test 0x%X failed\n",
|
pci_name(pdev), stat & 0x30);
|
wanxl_pci_remove_one(pdev);
|
return -ENODEV;
|
}
|
|
schedule();
|
}
|
|
/* get on-board memory size (PUTS detects no more than 4 MB) */
|
ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;
|
|
/* set up on-board RAM mapping */
|
mem_phy = pci_resource_start(pdev, 2);
|
|
|
/* sanity check the board's reported memory size */
|
if (ramsize < BUFFERS_ADDR +
|
(TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports) {
|
pr_warn("%s: no enough on-board RAM (%u bytes detected, %u bytes required)\n",
|
pci_name(pdev), ramsize,
|
BUFFERS_ADDR +
|
(TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports);
|
wanxl_pci_remove_one(pdev);
|
return -ENODEV;
|
}
|
|
if (wanxl_puts_command(card, MBX1_CMD_BSWAP)) {
|
pr_warn("%s: unable to Set Byte Swap Mode\n", pci_name(pdev));
|
wanxl_pci_remove_one(pdev);
|
return -ENODEV;
|
}
|
|
for (i = 0; i < RX_QUEUE_LENGTH; i++) {
|
struct sk_buff *skb = dev_alloc_skb(BUFFER_LENGTH);
|
card->rx_skbs[i] = skb;
|
if (skb)
|
card->status->rx_descs[i].address =
|
pci_map_single(card->pdev, skb->data,
|
BUFFER_LENGTH,
|
PCI_DMA_FROMDEVICE);
|
}
|
|
mem = ioremap_nocache(mem_phy, PDM_OFFSET + sizeof(firmware));
|
if (!mem) {
|
pr_err("ioremap() failed\n");
|
wanxl_pci_remove_one(pdev);
|
return -EFAULT;
|
}
|
|
for (i = 0; i < sizeof(firmware); i += 4)
|
writel(ntohl(*(__be32*)(firmware + i)), mem + PDM_OFFSET + i);
|
|
for (i = 0; i < ports; i++)
|
writel(card->status_address +
|
(void *)&card->status->port_status[i] -
|
(void *)card->status, mem + PDM_OFFSET + 4 + i * 4);
|
writel(card->status_address, mem + PDM_OFFSET + 20);
|
writel(PDM_OFFSET, mem);
|
iounmap(mem);
|
|
writel(0, card->plx + PLX_MAILBOX_5);
|
|
if (wanxl_puts_command(card, MBX1_CMD_ABORTJ)) {
|
pr_warn("%s: unable to Abort and Jump\n", pci_name(pdev));
|
wanxl_pci_remove_one(pdev);
|
return -ENODEV;
|
}
|
|
timeout = jiffies + 5 * HZ;
|
do {
|
if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0)
|
break;
|
schedule();
|
}while (time_after(timeout, jiffies));
|
|
if (!stat) {
|
pr_warn("%s: timeout while initializing card firmware\n",
|
pci_name(pdev));
|
wanxl_pci_remove_one(pdev);
|
return -ENODEV;
|
}
|
|
#if DETECT_RAM
|
ramsize = stat;
|
#endif
|
|
pr_info("%s: at 0x%X, %u KB of RAM at 0x%X, irq %u\n",
|
pci_name(pdev), plx_phy, ramsize / 1024, mem_phy, pdev->irq);
|
|
/* Allocate IRQ */
|
if (request_irq(pdev->irq, wanxl_intr, IRQF_SHARED, "wanXL", card)) {
|
pr_warn("%s: could not allocate IRQ%i\n",
|
pci_name(pdev), pdev->irq);
|
wanxl_pci_remove_one(pdev);
|
return -EBUSY;
|
}
|
card->irq = pdev->irq;
|
|
for (i = 0; i < ports; i++) {
|
hdlc_device *hdlc;
|
struct port *port = &card->ports[i];
|
struct net_device *dev = alloc_hdlcdev(port);
|
if (!dev) {
|
pr_err("%s: unable to allocate memory\n",
|
pci_name(pdev));
|
wanxl_pci_remove_one(pdev);
|
return -ENOMEM;
|
}
|
|
port->dev = dev;
|
hdlc = dev_to_hdlc(dev);
|
spin_lock_init(&port->lock);
|
dev->tx_queue_len = 50;
|
dev->netdev_ops = &wanxl_ops;
|
hdlc->attach = wanxl_attach;
|
hdlc->xmit = wanxl_xmit;
|
port->card = card;
|
port->node = i;
|
get_status(port)->clocking = CLOCK_EXT;
|
if (register_hdlc_device(dev)) {
|
pr_err("%s: unable to register hdlc device\n",
|
pci_name(pdev));
|
free_netdev(dev);
|
wanxl_pci_remove_one(pdev);
|
return -ENOBUFS;
|
}
|
card->n_ports++;
|
}
|
|
pr_info("%s: port", pci_name(pdev));
|
for (i = 0; i < ports; i++)
|
pr_cont("%s #%i: %s",
|
i ? "," : "", i, card->ports[i].dev->name);
|
pr_cont("\n");
|
|
for (i = 0; i < ports; i++)
|
wanxl_cable_intr(&card->ports[i]); /* get carrier status etc.*/
|
|
return 0;
|
}
|
|
static const struct pci_device_id wanxl_pci_tbl[] = {
|
{ PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL100, PCI_ANY_ID,
|
PCI_ANY_ID, 0, 0, 0 },
|
{ PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL200, PCI_ANY_ID,
|
PCI_ANY_ID, 0, 0, 0 },
|
{ PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL400, PCI_ANY_ID,
|
PCI_ANY_ID, 0, 0, 0 },
|
{ 0, }
|
};
|
|
|
static struct pci_driver wanxl_pci_driver = {
|
.name = "wanXL",
|
.id_table = wanxl_pci_tbl,
|
.probe = wanxl_pci_init_one,
|
.remove = wanxl_pci_remove_one,
|
};
|
|
|
static int __init wanxl_init_module(void)
|
{
|
#ifdef MODULE
|
pr_info("%s\n", version);
|
#endif
|
return pci_register_driver(&wanxl_pci_driver);
|
}
|
|
static void __exit wanxl_cleanup_module(void)
|
{
|
pci_unregister_driver(&wanxl_pci_driver);
|
}
|
|
|
MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
|
MODULE_DESCRIPTION("SBE Inc. wanXL serial port driver");
|
MODULE_LICENSE("GPL v2");
|
MODULE_DEVICE_TABLE(pci, wanxl_pci_tbl);
|
|
module_init(wanxl_init_module);
|
module_exit(wanxl_cleanup_module);
|
