/* Freescale QUICC Engine HDLC Device Driver
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*
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* Copyright 2016 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/hdlc.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/skbuff.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/stddef.h>
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#include <soc/fsl/qe/qe_tdm.h>
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#include <uapi/linux/if_arp.h>
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#include "fsl_ucc_hdlc.h"
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#define DRV_DESC "Freescale QE UCC HDLC Driver"
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#define DRV_NAME "ucc_hdlc"
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#define TDM_PPPOHT_SLIC_MAXIN
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static struct ucc_tdm_info utdm_primary_info = {
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.uf_info = {
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.tsa = 0,
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.cdp = 0,
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.cds = 1,
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.ctsp = 1,
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.ctss = 1,
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.revd = 0,
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.urfs = 256,
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.utfs = 256,
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.urfet = 128,
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.urfset = 192,
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.utfet = 128,
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.utftt = 0x40,
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.ufpt = 256,
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.mode = UCC_FAST_PROTOCOL_MODE_HDLC,
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.ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
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.tenc = UCC_FAST_TX_ENCODING_NRZ,
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.renc = UCC_FAST_RX_ENCODING_NRZ,
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.tcrc = UCC_FAST_16_BIT_CRC,
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.synl = UCC_FAST_SYNC_LEN_NOT_USED,
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},
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.si_info = {
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#ifdef TDM_PPPOHT_SLIC_MAXIN
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.simr_rfsd = 1,
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.simr_tfsd = 2,
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#else
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.simr_rfsd = 0,
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.simr_tfsd = 0,
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#endif
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.simr_crt = 0,
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.simr_sl = 0,
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.simr_ce = 1,
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.simr_fe = 1,
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.simr_gm = 0,
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},
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};
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static struct ucc_tdm_info utdm_info[UCC_MAX_NUM];
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static int uhdlc_init(struct ucc_hdlc_private *priv)
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{
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struct ucc_tdm_info *ut_info;
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struct ucc_fast_info *uf_info;
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u32 cecr_subblock;
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u16 bd_status;
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int ret, i;
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void *bd_buffer;
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dma_addr_t bd_dma_addr;
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u32 riptr;
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u32 tiptr;
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u32 gumr;
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ut_info = priv->ut_info;
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uf_info = &ut_info->uf_info;
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if (priv->tsa) {
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uf_info->tsa = 1;
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uf_info->ctsp = 1;
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}
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/* This sets HPM register in CMXUCR register which configures a
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* open drain connected HDLC bus
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*/
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if (priv->hdlc_bus)
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uf_info->brkpt_support = 1;
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uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
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UCC_HDLC_UCCE_TXB) << 16);
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ret = ucc_fast_init(uf_info, &priv->uccf);
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if (ret) {
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dev_err(priv->dev, "Failed to init uccf.");
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return ret;
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}
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priv->uf_regs = priv->uccf->uf_regs;
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ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
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/* Loopback mode */
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if (priv->loopback) {
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dev_info(priv->dev, "Loopback Mode\n");
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/* use the same clock when work in loopback */
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qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
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gumr = ioread32be(&priv->uf_regs->gumr);
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gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
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UCC_FAST_GUMR_TCI);
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gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
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iowrite32be(gumr, &priv->uf_regs->gumr);
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}
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/* Initialize SI */
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if (priv->tsa)
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ucc_tdm_init(priv->utdm, priv->ut_info);
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/* Write to QE CECR, UCCx channel to Stop Transmission */
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cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
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ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
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QE_CR_PROTOCOL_UNSPECIFIED, 0);
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/* Set UPSMR normal mode (need fixed)*/
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iowrite32be(0, &priv->uf_regs->upsmr);
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/* hdlc_bus mode */
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if (priv->hdlc_bus) {
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u32 upsmr;
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dev_info(priv->dev, "HDLC bus Mode\n");
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upsmr = ioread32be(&priv->uf_regs->upsmr);
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/* bus mode and retransmit enable, with collision window
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* set to 8 bytes
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*/
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upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
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UCC_HDLC_UPSMR_CW8;
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iowrite32be(upsmr, &priv->uf_regs->upsmr);
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/* explicitly disable CDS & CTSP */
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gumr = ioread32be(&priv->uf_regs->gumr);
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gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
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/* set automatic sync to explicitly ignore CD signal */
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gumr |= UCC_FAST_GUMR_SYNL_AUTO;
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iowrite32be(gumr, &priv->uf_regs->gumr);
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}
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priv->rx_ring_size = RX_BD_RING_LEN;
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priv->tx_ring_size = TX_BD_RING_LEN;
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/* Alloc Rx BD */
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priv->rx_bd_base = dma_alloc_coherent(priv->dev,
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RX_BD_RING_LEN * sizeof(struct qe_bd),
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&priv->dma_rx_bd, GFP_KERNEL);
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if (!priv->rx_bd_base) {
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dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n");
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ret = -ENOMEM;
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goto free_uccf;
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}
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/* Alloc Tx BD */
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priv->tx_bd_base = dma_alloc_coherent(priv->dev,
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TX_BD_RING_LEN * sizeof(struct qe_bd),
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&priv->dma_tx_bd, GFP_KERNEL);
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if (!priv->tx_bd_base) {
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dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n");
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ret = -ENOMEM;
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goto free_rx_bd;
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}
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/* Alloc parameter ram for ucc hdlc */
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priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
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ALIGNMENT_OF_UCC_HDLC_PRAM);
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if (IS_ERR_VALUE(priv->ucc_pram_offset)) {
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dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
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ret = -ENOMEM;
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goto free_tx_bd;
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}
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priv->rx_skbuff = kcalloc(priv->rx_ring_size,
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sizeof(*priv->rx_skbuff),
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GFP_KERNEL);
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if (!priv->rx_skbuff) {
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ret = -ENOMEM;
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goto free_ucc_pram;
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}
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priv->tx_skbuff = kcalloc(priv->tx_ring_size,
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sizeof(*priv->tx_skbuff),
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GFP_KERNEL);
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if (!priv->tx_skbuff) {
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ret = -ENOMEM;
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goto free_rx_skbuff;
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}
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priv->skb_curtx = 0;
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priv->skb_dirtytx = 0;
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priv->curtx_bd = priv->tx_bd_base;
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priv->dirty_tx = priv->tx_bd_base;
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priv->currx_bd = priv->rx_bd_base;
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priv->currx_bdnum = 0;
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/* init parameter base */
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cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
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ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
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QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
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priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
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qe_muram_addr(priv->ucc_pram_offset);
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/* Zero out parameter ram */
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memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param));
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/* Alloc riptr, tiptr */
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riptr = qe_muram_alloc(32, 32);
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if (IS_ERR_VALUE(riptr)) {
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dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
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ret = -ENOMEM;
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goto free_tx_skbuff;
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}
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tiptr = qe_muram_alloc(32, 32);
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if (IS_ERR_VALUE(tiptr)) {
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dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
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ret = -ENOMEM;
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goto free_riptr;
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}
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if (riptr != (u16)riptr || tiptr != (u16)tiptr) {
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dev_err(priv->dev, "MURAM allocation out of addressable range\n");
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ret = -ENOMEM;
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goto free_tiptr;
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}
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/* Set RIPTR, TIPTR */
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iowrite16be(riptr, &priv->ucc_pram->riptr);
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iowrite16be(tiptr, &priv->ucc_pram->tiptr);
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/* Set MRBLR */
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iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr);
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/* Set RBASE, TBASE */
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iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);
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iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);
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/* Set RSTATE, TSTATE */
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iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);
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iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);
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/* Set C_MASK, C_PRES for 16bit CRC */
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iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);
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iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);
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iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr);
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iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr);
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iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt);
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iowrite16be(DEFAULT_ADDR_MASK, &priv->ucc_pram->hmask);
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iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
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iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2);
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iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
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iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
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/* Get BD buffer */
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bd_buffer = dma_zalloc_coherent(priv->dev,
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(RX_BD_RING_LEN + TX_BD_RING_LEN) *
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MAX_RX_BUF_LENGTH,
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&bd_dma_addr, GFP_KERNEL);
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if (!bd_buffer) {
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dev_err(priv->dev, "Could not allocate buffer descriptors\n");
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ret = -ENOMEM;
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goto free_tiptr;
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}
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priv->rx_buffer = bd_buffer;
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priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
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priv->dma_rx_addr = bd_dma_addr;
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priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
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for (i = 0; i < RX_BD_RING_LEN; i++) {
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if (i < (RX_BD_RING_LEN - 1))
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bd_status = R_E_S | R_I_S;
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else
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bd_status = R_E_S | R_I_S | R_W_S;
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iowrite16be(bd_status, &priv->rx_bd_base[i].status);
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iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
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&priv->rx_bd_base[i].buf);
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}
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for (i = 0; i < TX_BD_RING_LEN; i++) {
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if (i < (TX_BD_RING_LEN - 1))
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bd_status = T_I_S | T_TC_S;
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else
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bd_status = T_I_S | T_TC_S | T_W_S;
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iowrite16be(bd_status, &priv->tx_bd_base[i].status);
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iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
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&priv->tx_bd_base[i].buf);
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}
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return 0;
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free_tiptr:
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qe_muram_free(tiptr);
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free_riptr:
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qe_muram_free(riptr);
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free_tx_skbuff:
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kfree(priv->tx_skbuff);
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free_rx_skbuff:
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kfree(priv->rx_skbuff);
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free_ucc_pram:
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qe_muram_free(priv->ucc_pram_offset);
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free_tx_bd:
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dma_free_coherent(priv->dev,
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TX_BD_RING_LEN * sizeof(struct qe_bd),
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priv->tx_bd_base, priv->dma_tx_bd);
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free_rx_bd:
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dma_free_coherent(priv->dev,
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RX_BD_RING_LEN * sizeof(struct qe_bd),
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priv->rx_bd_base, priv->dma_rx_bd);
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free_uccf:
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ucc_fast_free(priv->uccf);
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return ret;
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}
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static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
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{
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hdlc_device *hdlc = dev_to_hdlc(dev);
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struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv;
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struct qe_bd __iomem *bd;
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u16 bd_status;
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unsigned long flags;
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u16 *proto_head;
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switch (dev->type) {
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case ARPHRD_RAWHDLC:
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if (skb_headroom(skb) < HDLC_HEAD_LEN) {
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dev->stats.tx_dropped++;
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dev_kfree_skb(skb);
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netdev_err(dev, "No enough space for hdlc head\n");
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return -ENOMEM;
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}
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skb_push(skb, HDLC_HEAD_LEN);
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proto_head = (u16 *)skb->data;
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*proto_head = htons(DEFAULT_HDLC_HEAD);
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dev->stats.tx_bytes += skb->len;
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break;
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case ARPHRD_PPP:
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proto_head = (u16 *)skb->data;
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if (*proto_head != htons(DEFAULT_PPP_HEAD)) {
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dev->stats.tx_dropped++;
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dev_kfree_skb(skb);
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netdev_err(dev, "Wrong ppp header\n");
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return -ENOMEM;
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}
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dev->stats.tx_bytes += skb->len;
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break;
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default:
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dev->stats.tx_dropped++;
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dev_kfree_skb(skb);
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return -ENOMEM;
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}
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spin_lock_irqsave(&priv->lock, flags);
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/* Start from the next BD that should be filled */
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bd = priv->curtx_bd;
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bd_status = ioread16be(&bd->status);
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/* Save the skb pointer so we can free it later */
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priv->tx_skbuff[priv->skb_curtx] = skb;
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/* Update the current skb pointer (wrapping if this was the last) */
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priv->skb_curtx =
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(priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
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/* copy skb data to tx buffer for sdma processing */
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memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
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skb->data, skb->len);
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/* set bd status and length */
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bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
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iowrite16be(skb->len, &bd->length);
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iowrite16be(bd_status, &bd->status);
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/* Move to next BD in the ring */
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if (!(bd_status & T_W_S))
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bd += 1;
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else
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bd = priv->tx_bd_base;
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if (bd == priv->dirty_tx) {
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if (!netif_queue_stopped(dev))
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netif_stop_queue(dev);
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}
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priv->curtx_bd = bd;
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spin_unlock_irqrestore(&priv->lock, flags);
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return NETDEV_TX_OK;
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}
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static int hdlc_tx_done(struct ucc_hdlc_private *priv)
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{
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/* Start from the next BD that should be filled */
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struct net_device *dev = priv->ndev;
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struct qe_bd *bd; /* BD pointer */
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u16 bd_status;
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bd = priv->dirty_tx;
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bd_status = ioread16be(&bd->status);
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/* Normal processing. */
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while ((bd_status & T_R_S) == 0) {
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struct sk_buff *skb;
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/* BD contains already transmitted buffer. */
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/* Handle the transmitted buffer and release */
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/* the BD to be used with the current frame */
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skb = priv->tx_skbuff[priv->skb_dirtytx];
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if (!skb)
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break;
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dev->stats.tx_packets++;
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memset(priv->tx_buffer +
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(be32_to_cpu(bd->buf) - priv->dma_tx_addr),
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0, skb->len);
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dev_kfree_skb_irq(skb);
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priv->tx_skbuff[priv->skb_dirtytx] = NULL;
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priv->skb_dirtytx =
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(priv->skb_dirtytx +
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1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
|
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/* We freed a buffer, so now we can restart transmission */
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if (netif_queue_stopped(dev))
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netif_wake_queue(dev);
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/* Advance the confirmation BD pointer */
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if (!(bd_status & T_W_S))
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bd += 1;
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else
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bd = priv->tx_bd_base;
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bd_status = ioread16be(&bd->status);
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}
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priv->dirty_tx = bd;
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return 0;
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}
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static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
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{
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struct net_device *dev = priv->ndev;
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struct sk_buff *skb = NULL;
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hdlc_device *hdlc = dev_to_hdlc(dev);
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struct qe_bd *bd;
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u16 bd_status;
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u16 length, howmany = 0;
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u8 *bdbuffer;
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bd = priv->currx_bd;
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bd_status = ioread16be(&bd->status);
|
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/* while there are received buffers and BD is full (~R_E) */
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while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) {
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if (bd_status & R_OV_S)
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dev->stats.rx_over_errors++;
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if (bd_status & R_CR_S) {
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dev->stats.rx_crc_errors++;
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dev->stats.rx_dropped++;
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goto recycle;
|
}
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bdbuffer = priv->rx_buffer +
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(priv->currx_bdnum * MAX_RX_BUF_LENGTH);
|
length = ioread16be(&bd->length);
|
|
switch (dev->type) {
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case ARPHRD_RAWHDLC:
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bdbuffer += HDLC_HEAD_LEN;
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length -= (HDLC_HEAD_LEN + HDLC_CRC_SIZE);
|
|
skb = dev_alloc_skb(length);
|
if (!skb) {
|
dev->stats.rx_dropped++;
|
return -ENOMEM;
|
}
|
|
skb_put(skb, length);
|
skb->len = length;
|
skb->dev = dev;
|
memcpy(skb->data, bdbuffer, length);
|
break;
|
|
case ARPHRD_PPP:
|
length -= HDLC_CRC_SIZE;
|
|
skb = dev_alloc_skb(length);
|
if (!skb) {
|
dev->stats.rx_dropped++;
|
return -ENOMEM;
|
}
|
|
skb_put(skb, length);
|
skb->len = length;
|
skb->dev = dev;
|
memcpy(skb->data, bdbuffer, length);
|
break;
|
}
|
|
dev->stats.rx_packets++;
|
dev->stats.rx_bytes += skb->len;
|
howmany++;
|
if (hdlc->proto)
|
skb->protocol = hdlc_type_trans(skb, dev);
|
netif_receive_skb(skb);
|
|
recycle:
|
iowrite16be(bd_status | R_E_S | R_I_S, &bd->status);
|
|
/* update to point at the next bd */
|
if (bd_status & R_W_S) {
|
priv->currx_bdnum = 0;
|
bd = priv->rx_bd_base;
|
} else {
|
if (priv->currx_bdnum < (RX_BD_RING_LEN - 1))
|
priv->currx_bdnum += 1;
|
else
|
priv->currx_bdnum = RX_BD_RING_LEN - 1;
|
|
bd += 1;
|
}
|
|
bd_status = ioread16be(&bd->status);
|
}
|
|
priv->currx_bd = bd;
|
return howmany;
|
}
|
|
static int ucc_hdlc_poll(struct napi_struct *napi, int budget)
|
{
|
struct ucc_hdlc_private *priv = container_of(napi,
|
struct ucc_hdlc_private,
|
napi);
|
int howmany;
|
|
/* Tx event processing */
|
spin_lock(&priv->lock);
|
hdlc_tx_done(priv);
|
spin_unlock(&priv->lock);
|
|
howmany = 0;
|
howmany += hdlc_rx_done(priv, budget - howmany);
|
|
if (howmany < budget) {
|
napi_complete_done(napi, howmany);
|
qe_setbits32(priv->uccf->p_uccm,
|
(UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
|
}
|
|
return howmany;
|
}
|
|
static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id)
|
{
|
struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id;
|
struct net_device *dev = priv->ndev;
|
struct ucc_fast_private *uccf;
|
struct ucc_tdm_info *ut_info;
|
u32 ucce;
|
u32 uccm;
|
|
ut_info = priv->ut_info;
|
uccf = priv->uccf;
|
|
ucce = ioread32be(uccf->p_ucce);
|
uccm = ioread32be(uccf->p_uccm);
|
ucce &= uccm;
|
iowrite32be(ucce, uccf->p_ucce);
|
if (!ucce)
|
return IRQ_NONE;
|
|
if ((ucce >> 16) & (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)) {
|
if (napi_schedule_prep(&priv->napi)) {
|
uccm &= ~((UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)
|
<< 16);
|
iowrite32be(uccm, uccf->p_uccm);
|
__napi_schedule(&priv->napi);
|
}
|
}
|
|
/* Errors and other events */
|
if (ucce >> 16 & UCC_HDLC_UCCE_BSY)
|
dev->stats.rx_errors++;
|
if (ucce >> 16 & UCC_HDLC_UCCE_TXE)
|
dev->stats.tx_errors++;
|
|
return IRQ_HANDLED;
|
}
|
|
static int uhdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
{
|
const size_t size = sizeof(te1_settings);
|
te1_settings line;
|
struct ucc_hdlc_private *priv = netdev_priv(dev);
|
|
if (cmd != SIOCWANDEV)
|
return hdlc_ioctl(dev, ifr, cmd);
|
|
switch (ifr->ifr_settings.type) {
|
case IF_GET_IFACE:
|
ifr->ifr_settings.type = IF_IFACE_E1;
|
if (ifr->ifr_settings.size < size) {
|
ifr->ifr_settings.size = size; /* data size wanted */
|
return -ENOBUFS;
|
}
|
memset(&line, 0, sizeof(line));
|
line.clock_type = priv->clocking;
|
|
if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size))
|
return -EFAULT;
|
return 0;
|
|
default:
|
return hdlc_ioctl(dev, ifr, cmd);
|
}
|
}
|
|
static int uhdlc_open(struct net_device *dev)
|
{
|
u32 cecr_subblock;
|
hdlc_device *hdlc = dev_to_hdlc(dev);
|
struct ucc_hdlc_private *priv = hdlc->priv;
|
struct ucc_tdm *utdm = priv->utdm;
|
|
if (priv->hdlc_busy != 1) {
|
if (request_irq(priv->ut_info->uf_info.irq,
|
ucc_hdlc_irq_handler, 0, "hdlc", priv))
|
return -ENODEV;
|
|
cecr_subblock = ucc_fast_get_qe_cr_subblock(
|
priv->ut_info->uf_info.ucc_num);
|
|
qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
|
QE_CR_PROTOCOL_UNSPECIFIED, 0);
|
|
ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
|
|
/* Enable the TDM port */
|
if (priv->tsa)
|
utdm->si_regs->siglmr1_h |= (0x1 << utdm->tdm_port);
|
|
priv->hdlc_busy = 1;
|
netif_device_attach(priv->ndev);
|
napi_enable(&priv->napi);
|
netif_start_queue(dev);
|
hdlc_open(dev);
|
}
|
|
return 0;
|
}
|
|
static void uhdlc_memclean(struct ucc_hdlc_private *priv)
|
{
|
qe_muram_free(priv->ucc_pram->riptr);
|
qe_muram_free(priv->ucc_pram->tiptr);
|
|
if (priv->rx_bd_base) {
|
dma_free_coherent(priv->dev,
|
RX_BD_RING_LEN * sizeof(struct qe_bd),
|
priv->rx_bd_base, priv->dma_rx_bd);
|
|
priv->rx_bd_base = NULL;
|
priv->dma_rx_bd = 0;
|
}
|
|
if (priv->tx_bd_base) {
|
dma_free_coherent(priv->dev,
|
TX_BD_RING_LEN * sizeof(struct qe_bd),
|
priv->tx_bd_base, priv->dma_tx_bd);
|
|
priv->tx_bd_base = NULL;
|
priv->dma_tx_bd = 0;
|
}
|
|
if (priv->ucc_pram) {
|
qe_muram_free(priv->ucc_pram_offset);
|
priv->ucc_pram = NULL;
|
priv->ucc_pram_offset = 0;
|
}
|
|
kfree(priv->rx_skbuff);
|
priv->rx_skbuff = NULL;
|
|
kfree(priv->tx_skbuff);
|
priv->tx_skbuff = NULL;
|
|
if (priv->uf_regs) {
|
iounmap(priv->uf_regs);
|
priv->uf_regs = NULL;
|
}
|
|
if (priv->uccf) {
|
ucc_fast_free(priv->uccf);
|
priv->uccf = NULL;
|
}
|
|
if (priv->rx_buffer) {
|
dma_free_coherent(priv->dev,
|
RX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
|
priv->rx_buffer, priv->dma_rx_addr);
|
priv->rx_buffer = NULL;
|
priv->dma_rx_addr = 0;
|
}
|
|
if (priv->tx_buffer) {
|
dma_free_coherent(priv->dev,
|
TX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
|
priv->tx_buffer, priv->dma_tx_addr);
|
priv->tx_buffer = NULL;
|
priv->dma_tx_addr = 0;
|
}
|
}
|
|
static int uhdlc_close(struct net_device *dev)
|
{
|
struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
|
struct ucc_tdm *utdm = priv->utdm;
|
u32 cecr_subblock;
|
|
napi_disable(&priv->napi);
|
cecr_subblock = ucc_fast_get_qe_cr_subblock(
|
priv->ut_info->uf_info.ucc_num);
|
|
qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
|
(u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
|
qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock,
|
(u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
|
|
if (priv->tsa)
|
utdm->si_regs->siglmr1_h &= ~(0x1 << utdm->tdm_port);
|
|
ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
|
|
free_irq(priv->ut_info->uf_info.irq, priv);
|
netif_stop_queue(dev);
|
priv->hdlc_busy = 0;
|
|
return 0;
|
}
|
|
static int ucc_hdlc_attach(struct net_device *dev, unsigned short encoding,
|
unsigned short parity)
|
{
|
struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
|
|
if (encoding != ENCODING_NRZ &&
|
encoding != ENCODING_NRZI)
|
return -EINVAL;
|
|
if (parity != PARITY_NONE &&
|
parity != PARITY_CRC32_PR1_CCITT &&
|
parity != PARITY_CRC16_PR1_CCITT)
|
return -EINVAL;
|
|
priv->encoding = encoding;
|
priv->parity = parity;
|
|
return 0;
|
}
|
|
#ifdef CONFIG_PM
|
static void store_clk_config(struct ucc_hdlc_private *priv)
|
{
|
struct qe_mux *qe_mux_reg = &qe_immr->qmx;
|
|
/* store si clk */
|
priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h);
|
priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l);
|
|
/* store si sync */
|
priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr);
|
|
/* store ucc clk */
|
memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32));
|
}
|
|
static void resume_clk_config(struct ucc_hdlc_private *priv)
|
{
|
struct qe_mux *qe_mux_reg = &qe_immr->qmx;
|
|
memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32));
|
|
iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h);
|
iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l);
|
|
iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr);
|
}
|
|
static int uhdlc_suspend(struct device *dev)
|
{
|
struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
|
struct ucc_tdm_info *ut_info;
|
struct ucc_fast __iomem *uf_regs;
|
|
if (!priv)
|
return -EINVAL;
|
|
if (!netif_running(priv->ndev))
|
return 0;
|
|
netif_device_detach(priv->ndev);
|
napi_disable(&priv->napi);
|
|
ut_info = priv->ut_info;
|
uf_regs = priv->uf_regs;
|
|
/* backup gumr guemr*/
|
priv->gumr = ioread32be(&uf_regs->gumr);
|
priv->guemr = ioread8(&uf_regs->guemr);
|
|
priv->ucc_pram_bak = kmalloc(sizeof(*priv->ucc_pram_bak),
|
GFP_KERNEL);
|
if (!priv->ucc_pram_bak)
|
return -ENOMEM;
|
|
/* backup HDLC parameter */
|
memcpy_fromio(priv->ucc_pram_bak, priv->ucc_pram,
|
sizeof(struct ucc_hdlc_param));
|
|
/* store the clk configuration */
|
store_clk_config(priv);
|
|
/* save power */
|
ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
|
|
return 0;
|
}
|
|
static int uhdlc_resume(struct device *dev)
|
{
|
struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
|
struct ucc_tdm *utdm;
|
struct ucc_tdm_info *ut_info;
|
struct ucc_fast __iomem *uf_regs;
|
struct ucc_fast_private *uccf;
|
struct ucc_fast_info *uf_info;
|
int ret, i;
|
u32 cecr_subblock;
|
u16 bd_status;
|
|
if (!priv)
|
return -EINVAL;
|
|
if (!netif_running(priv->ndev))
|
return 0;
|
|
utdm = priv->utdm;
|
ut_info = priv->ut_info;
|
uf_info = &ut_info->uf_info;
|
uf_regs = priv->uf_regs;
|
uccf = priv->uccf;
|
|
/* restore gumr guemr */
|
iowrite8(priv->guemr, &uf_regs->guemr);
|
iowrite32be(priv->gumr, &uf_regs->gumr);
|
|
/* Set Virtual Fifo registers */
|
iowrite16be(uf_info->urfs, &uf_regs->urfs);
|
iowrite16be(uf_info->urfet, &uf_regs->urfet);
|
iowrite16be(uf_info->urfset, &uf_regs->urfset);
|
iowrite16be(uf_info->utfs, &uf_regs->utfs);
|
iowrite16be(uf_info->utfet, &uf_regs->utfet);
|
iowrite16be(uf_info->utftt, &uf_regs->utftt);
|
/* utfb, urfb are offsets from MURAM base */
|
iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);
|
iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);
|
|
/* Rx Tx and sync clock routing */
|
resume_clk_config(priv);
|
|
iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
|
iowrite32be(0xffffffff, &uf_regs->ucce);
|
|
ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
|
|
/* rebuild SIRAM */
|
if (priv->tsa)
|
ucc_tdm_init(priv->utdm, priv->ut_info);
|
|
/* Write to QE CECR, UCCx channel to Stop Transmission */
|
cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
|
ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
|
(u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
|
|
/* Set UPSMR normal mode */
|
iowrite32be(0, &uf_regs->upsmr);
|
|
/* init parameter base */
|
cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
|
ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
|
QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
|
|
priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
|
qe_muram_addr(priv->ucc_pram_offset);
|
|
/* restore ucc parameter */
|
memcpy_toio(priv->ucc_pram, priv->ucc_pram_bak,
|
sizeof(struct ucc_hdlc_param));
|
kfree(priv->ucc_pram_bak);
|
|
/* rebuild BD entry */
|
for (i = 0; i < RX_BD_RING_LEN; i++) {
|
if (i < (RX_BD_RING_LEN - 1))
|
bd_status = R_E_S | R_I_S;
|
else
|
bd_status = R_E_S | R_I_S | R_W_S;
|
|
iowrite16be(bd_status, &priv->rx_bd_base[i].status);
|
iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
|
&priv->rx_bd_base[i].buf);
|
}
|
|
for (i = 0; i < TX_BD_RING_LEN; i++) {
|
if (i < (TX_BD_RING_LEN - 1))
|
bd_status = T_I_S | T_TC_S;
|
else
|
bd_status = T_I_S | T_TC_S | T_W_S;
|
|
iowrite16be(bd_status, &priv->tx_bd_base[i].status);
|
iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
|
&priv->tx_bd_base[i].buf);
|
}
|
|
/* if hdlc is busy enable TX and RX */
|
if (priv->hdlc_busy == 1) {
|
cecr_subblock = ucc_fast_get_qe_cr_subblock(
|
priv->ut_info->uf_info.ucc_num);
|
|
qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
|
(u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
|
|
ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
|
|
/* Enable the TDM port */
|
if (priv->tsa)
|
utdm->si_regs->siglmr1_h |= (0x1 << utdm->tdm_port);
|
}
|
|
napi_enable(&priv->napi);
|
netif_device_attach(priv->ndev);
|
|
return 0;
|
}
|
|
static const struct dev_pm_ops uhdlc_pm_ops = {
|
.suspend = uhdlc_suspend,
|
.resume = uhdlc_resume,
|
.freeze = uhdlc_suspend,
|
.thaw = uhdlc_resume,
|
};
|
|
#define HDLC_PM_OPS (&uhdlc_pm_ops)
|
|
#else
|
|
#define HDLC_PM_OPS NULL
|
|
#endif
|
static const struct net_device_ops uhdlc_ops = {
|
.ndo_open = uhdlc_open,
|
.ndo_stop = uhdlc_close,
|
.ndo_start_xmit = hdlc_start_xmit,
|
.ndo_do_ioctl = uhdlc_ioctl,
|
};
|
|
static int ucc_hdlc_probe(struct platform_device *pdev)
|
{
|
struct device_node *np = pdev->dev.of_node;
|
struct ucc_hdlc_private *uhdlc_priv = NULL;
|
struct ucc_tdm_info *ut_info;
|
struct ucc_tdm *utdm = NULL;
|
struct resource res;
|
struct net_device *dev;
|
hdlc_device *hdlc;
|
int ucc_num;
|
const char *sprop;
|
int ret;
|
u32 val;
|
|
ret = of_property_read_u32_index(np, "cell-index", 0, &val);
|
if (ret) {
|
dev_err(&pdev->dev, "Invalid ucc property\n");
|
return -ENODEV;
|
}
|
|
ucc_num = val - 1;
|
if ((ucc_num > 3) || (ucc_num < 0)) {
|
dev_err(&pdev->dev, ": Invalid UCC num\n");
|
return -EINVAL;
|
}
|
|
memcpy(&utdm_info[ucc_num], &utdm_primary_info,
|
sizeof(utdm_primary_info));
|
|
ut_info = &utdm_info[ucc_num];
|
ut_info->uf_info.ucc_num = ucc_num;
|
|
sprop = of_get_property(np, "rx-clock-name", NULL);
|
if (sprop) {
|
ut_info->uf_info.rx_clock = qe_clock_source(sprop);
|
if ((ut_info->uf_info.rx_clock < QE_CLK_NONE) ||
|
(ut_info->uf_info.rx_clock > QE_CLK24)) {
|
dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
|
return -EINVAL;
|
}
|
} else {
|
dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
|
return -EINVAL;
|
}
|
|
sprop = of_get_property(np, "tx-clock-name", NULL);
|
if (sprop) {
|
ut_info->uf_info.tx_clock = qe_clock_source(sprop);
|
if ((ut_info->uf_info.tx_clock < QE_CLK_NONE) ||
|
(ut_info->uf_info.tx_clock > QE_CLK24)) {
|
dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
|
return -EINVAL;
|
}
|
} else {
|
dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
|
return -EINVAL;
|
}
|
|
ret = of_address_to_resource(np, 0, &res);
|
if (ret)
|
return -EINVAL;
|
|
ut_info->uf_info.regs = res.start;
|
ut_info->uf_info.irq = irq_of_parse_and_map(np, 0);
|
|
uhdlc_priv = kzalloc(sizeof(*uhdlc_priv), GFP_KERNEL);
|
if (!uhdlc_priv) {
|
return -ENOMEM;
|
}
|
|
dev_set_drvdata(&pdev->dev, uhdlc_priv);
|
uhdlc_priv->dev = &pdev->dev;
|
uhdlc_priv->ut_info = ut_info;
|
|
if (of_get_property(np, "fsl,tdm-interface", NULL))
|
uhdlc_priv->tsa = 1;
|
|
if (of_get_property(np, "fsl,ucc-internal-loopback", NULL))
|
uhdlc_priv->loopback = 1;
|
|
if (of_get_property(np, "fsl,hdlc-bus", NULL))
|
uhdlc_priv->hdlc_bus = 1;
|
|
if (uhdlc_priv->tsa == 1) {
|
utdm = kzalloc(sizeof(*utdm), GFP_KERNEL);
|
if (!utdm) {
|
ret = -ENOMEM;
|
dev_err(&pdev->dev, "No mem to alloc ucc tdm data\n");
|
goto free_uhdlc_priv;
|
}
|
uhdlc_priv->utdm = utdm;
|
ret = ucc_of_parse_tdm(np, utdm, ut_info);
|
if (ret)
|
goto free_utdm;
|
}
|
|
ret = uhdlc_init(uhdlc_priv);
|
if (ret) {
|
dev_err(&pdev->dev, "Failed to init uhdlc\n");
|
goto free_utdm;
|
}
|
|
dev = alloc_hdlcdev(uhdlc_priv);
|
if (!dev) {
|
ret = -ENOMEM;
|
pr_err("ucc_hdlc: unable to allocate memory\n");
|
goto undo_uhdlc_init;
|
}
|
|
uhdlc_priv->ndev = dev;
|
hdlc = dev_to_hdlc(dev);
|
dev->tx_queue_len = 16;
|
dev->netdev_ops = &uhdlc_ops;
|
hdlc->attach = ucc_hdlc_attach;
|
hdlc->xmit = ucc_hdlc_tx;
|
netif_napi_add(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32);
|
if (register_hdlc_device(dev)) {
|
ret = -ENOBUFS;
|
pr_err("ucc_hdlc: unable to register hdlc device\n");
|
goto free_dev;
|
}
|
|
return 0;
|
|
free_dev:
|
free_netdev(dev);
|
undo_uhdlc_init:
|
free_utdm:
|
if (uhdlc_priv->tsa)
|
kfree(utdm);
|
free_uhdlc_priv:
|
kfree(uhdlc_priv);
|
return ret;
|
}
|
|
static int ucc_hdlc_remove(struct platform_device *pdev)
|
{
|
struct ucc_hdlc_private *priv = dev_get_drvdata(&pdev->dev);
|
|
uhdlc_memclean(priv);
|
|
if (priv->utdm->si_regs) {
|
iounmap(priv->utdm->si_regs);
|
priv->utdm->si_regs = NULL;
|
}
|
|
if (priv->utdm->siram) {
|
iounmap(priv->utdm->siram);
|
priv->utdm->siram = NULL;
|
}
|
kfree(priv);
|
|
dev_info(&pdev->dev, "UCC based hdlc module removed\n");
|
|
return 0;
|
}
|
|
static const struct of_device_id fsl_ucc_hdlc_of_match[] = {
|
{
|
.compatible = "fsl,ucc-hdlc",
|
},
|
{},
|
};
|
|
MODULE_DEVICE_TABLE(of, fsl_ucc_hdlc_of_match);
|
|
static struct platform_driver ucc_hdlc_driver = {
|
.probe = ucc_hdlc_probe,
|
.remove = ucc_hdlc_remove,
|
.driver = {
|
.name = DRV_NAME,
|
.pm = HDLC_PM_OPS,
|
.of_match_table = fsl_ucc_hdlc_of_match,
|
},
|
};
|
|
module_platform_driver(ucc_hdlc_driver);
|
MODULE_LICENSE("GPL");
|
