/*
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* Moxa C101 synchronous serial card driver for Linux
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*
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* Copyright (C) 2000-2003 Krzysztof Halasa <khc@pm.waw.pl>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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* For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>
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*
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* Sources of information:
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* Hitachi HD64570 SCA User's Manual
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* Moxa C101 User's Manual
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/capability.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/moduleparam.h>
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#include <linux/netdevice.h>
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#include <linux/hdlc.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include "hd64570.h"
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static const char* version = "Moxa C101 driver version: 1.15";
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static const char* devname = "C101";
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#undef DEBUG_PKT
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#define DEBUG_RINGS
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#define C101_PAGE 0x1D00
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#define C101_DTR 0x1E00
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#define C101_SCA 0x1F00
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#define C101_WINDOW_SIZE 0x2000
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#define C101_MAPPED_RAM_SIZE 0x4000
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#define RAM_SIZE (256 * 1024)
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#define TX_RING_BUFFERS 10
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#define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) / \
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(sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS)
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#define CLOCK_BASE 9830400 /* 9.8304 MHz */
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#define PAGE0_ALWAYS_MAPPED
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static char *hw; /* pointer to hw=xxx command line string */
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typedef struct card_s {
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struct net_device *dev;
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spinlock_t lock; /* TX lock */
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u8 __iomem *win0base; /* ISA window base address */
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u32 phy_winbase; /* ISA physical base address */
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sync_serial_settings settings;
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int rxpart; /* partial frame received, next frame invalid*/
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unsigned short encoding;
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unsigned short parity;
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u16 rx_ring_buffers; /* number of buffers in a ring */
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u16 tx_ring_buffers;
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u16 buff_offset; /* offset of first buffer of first channel */
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u16 rxin; /* rx ring buffer 'in' pointer */
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u16 txin; /* tx ring buffer 'in' and 'last' pointers */
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u16 txlast;
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u8 rxs, txs, tmc; /* SCA registers */
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u8 irq; /* IRQ (3-15) */
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u8 page;
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struct card_s *next_card;
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}card_t;
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typedef card_t port_t;
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static card_t *first_card;
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static card_t **new_card = &first_card;
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#define sca_in(reg, card) readb((card)->win0base + C101_SCA + (reg))
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#define sca_out(value, reg, card) writeb(value, (card)->win0base + C101_SCA + (reg))
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#define sca_inw(reg, card) readw((card)->win0base + C101_SCA + (reg))
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/* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */
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#define sca_outw(value, reg, card) do { \
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writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \
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writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg + 1));\
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} while(0)
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#define port_to_card(port) (port)
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#define log_node(port) (0)
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#define phy_node(port) (0)
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#define winsize(card) (C101_WINDOW_SIZE)
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#define win0base(card) ((card)->win0base)
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#define winbase(card) ((card)->win0base + 0x2000)
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#define get_port(card, port) (card)
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static void sca_msci_intr(port_t *port);
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static inline u8 sca_get_page(card_t *card)
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{
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return card->page;
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}
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static inline void openwin(card_t *card, u8 page)
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{
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card->page = page;
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writeb(page, card->win0base + C101_PAGE);
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}
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#include "hd64570.c"
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static inline void set_carrier(port_t *port)
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{
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if (!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD))
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netif_carrier_on(port_to_dev(port));
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else
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netif_carrier_off(port_to_dev(port));
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}
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static void sca_msci_intr(port_t *port)
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{
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u8 stat = sca_in(MSCI0_OFFSET + ST1, port); /* read MSCI ST1 status */
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/* Reset MSCI TX underrun and CDCD (ignored) status bit */
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sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port);
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if (stat & ST1_UDRN) {
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/* TX Underrun error detected */
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port_to_dev(port)->stats.tx_errors++;
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port_to_dev(port)->stats.tx_fifo_errors++;
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}
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stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */
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/* Reset MSCI CDCD status bit - uses ch#2 DCD input */
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sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port);
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if (stat & ST1_CDCD)
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set_carrier(port);
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}
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static void c101_set_iface(port_t *port)
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{
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u8 rxs = port->rxs & CLK_BRG_MASK;
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u8 txs = port->txs & CLK_BRG_MASK;
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switch(port->settings.clock_type) {
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case CLOCK_INT:
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rxs |= CLK_BRG_RX; /* TX clock */
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txs |= CLK_RXCLK_TX; /* BRG output */
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break;
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case CLOCK_TXINT:
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rxs |= CLK_LINE_RX; /* RXC input */
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txs |= CLK_BRG_TX; /* BRG output */
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break;
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case CLOCK_TXFROMRX:
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rxs |= CLK_LINE_RX; /* RXC input */
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txs |= CLK_RXCLK_TX; /* RX clock */
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break;
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default: /* EXTernal clock */
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rxs |= CLK_LINE_RX; /* RXC input */
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txs |= CLK_LINE_TX; /* TXC input */
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}
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port->rxs = rxs;
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port->txs = txs;
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sca_out(rxs, MSCI1_OFFSET + RXS, port);
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sca_out(txs, MSCI1_OFFSET + TXS, port);
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sca_set_port(port);
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}
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static int c101_open(struct net_device *dev)
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{
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port_t *port = dev_to_port(dev);
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int result;
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result = hdlc_open(dev);
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if (result)
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return result;
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writeb(1, port->win0base + C101_DTR);
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sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */
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sca_open(dev);
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/* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */
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sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
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sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);
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set_carrier(port);
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/* enable MSCI1 CDCD interrupt */
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sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
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sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);
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sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */
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c101_set_iface(port);
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return 0;
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}
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static int c101_close(struct net_device *dev)
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{
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port_t *port = dev_to_port(dev);
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sca_close(dev);
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writeb(0, port->win0base + C101_DTR);
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sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
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hdlc_close(dev);
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return 0;
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}
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static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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{
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const size_t size = sizeof(sync_serial_settings);
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sync_serial_settings new_line;
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sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
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port_t *port = dev_to_port(dev);
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#ifdef DEBUG_RINGS
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if (cmd == SIOCDEVPRIVATE) {
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sca_dump_rings(dev);
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printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n",
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sca_in(MSCI1_OFFSET + ST0, port),
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sca_in(MSCI1_OFFSET + ST1, port),
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sca_in(MSCI1_OFFSET + ST2, port),
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sca_in(MSCI1_OFFSET + ST3, port));
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return 0;
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}
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#endif
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if (cmd != SIOCWANDEV)
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return hdlc_ioctl(dev, ifr, cmd);
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switch(ifr->ifr_settings.type) {
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case IF_GET_IFACE:
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ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
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if (ifr->ifr_settings.size < size) {
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ifr->ifr_settings.size = size; /* data size wanted */
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return -ENOBUFS;
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}
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if (copy_to_user(line, &port->settings, size))
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return -EFAULT;
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return 0;
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case IF_IFACE_SYNC_SERIAL:
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if(!capable(CAP_NET_ADMIN))
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return -EPERM;
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if (copy_from_user(&new_line, line, size))
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return -EFAULT;
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if (new_line.clock_type != CLOCK_EXT &&
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new_line.clock_type != CLOCK_TXFROMRX &&
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new_line.clock_type != CLOCK_INT &&
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new_line.clock_type != CLOCK_TXINT)
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return -EINVAL; /* No such clock setting */
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if (new_line.loopback != 0 && new_line.loopback != 1)
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return -EINVAL;
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memcpy(&port->settings, &new_line, size); /* Update settings */
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c101_set_iface(port);
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return 0;
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default:
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return hdlc_ioctl(dev, ifr, cmd);
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}
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}
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static void c101_destroy_card(card_t *card)
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{
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readb(card->win0base + C101_PAGE); /* Resets SCA? */
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if (card->irq)
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free_irq(card->irq, card);
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if (card->win0base) {
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iounmap(card->win0base);
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release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE);
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}
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free_netdev(card->dev);
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kfree(card);
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}
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static const struct net_device_ops c101_ops = {
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.ndo_open = c101_open,
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.ndo_stop = c101_close,
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.ndo_start_xmit = hdlc_start_xmit,
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.ndo_do_ioctl = c101_ioctl,
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};
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static int __init c101_run(unsigned long irq, unsigned long winbase)
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{
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struct net_device *dev;
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hdlc_device *hdlc;
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card_t *card;
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int result;
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if (irq<3 || irq>15 || irq == 6) /* FIXME */ {
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pr_err("invalid IRQ value\n");
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return -ENODEV;
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}
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if (winbase < 0xC0000 || winbase > 0xDFFFF || (winbase & 0x3FFF) !=0) {
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pr_err("invalid RAM value\n");
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return -ENODEV;
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}
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card = kzalloc(sizeof(card_t), GFP_KERNEL);
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if (card == NULL)
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return -ENOBUFS;
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card->dev = alloc_hdlcdev(card);
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if (!card->dev) {
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pr_err("unable to allocate memory\n");
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kfree(card);
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return -ENOBUFS;
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}
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if (request_irq(irq, sca_intr, 0, devname, card)) {
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pr_err("could not allocate IRQ\n");
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c101_destroy_card(card);
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return -EBUSY;
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}
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card->irq = irq;
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if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) {
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pr_err("could not request RAM window\n");
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c101_destroy_card(card);
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return -EBUSY;
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}
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card->phy_winbase = winbase;
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card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE);
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if (!card->win0base) {
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pr_err("could not map I/O address\n");
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c101_destroy_card(card);
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return -EFAULT;
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}
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card->tx_ring_buffers = TX_RING_BUFFERS;
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card->rx_ring_buffers = RX_RING_BUFFERS;
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card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */
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readb(card->win0base + C101_PAGE); /* Resets SCA? */
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udelay(100);
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writeb(0, card->win0base + C101_PAGE);
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writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */
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sca_init(card, 0);
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dev = port_to_dev(card);
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hdlc = dev_to_hdlc(dev);
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spin_lock_init(&card->lock);
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dev->irq = irq;
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dev->mem_start = winbase;
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dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1;
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dev->tx_queue_len = 50;
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dev->netdev_ops = &c101_ops;
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hdlc->attach = sca_attach;
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hdlc->xmit = sca_xmit;
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card->settings.clock_type = CLOCK_EXT;
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result = register_hdlc_device(dev);
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if (result) {
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pr_warn("unable to register hdlc device\n");
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c101_destroy_card(card);
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return result;
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}
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sca_init_port(card); /* Set up C101 memory */
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set_carrier(card);
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netdev_info(dev, "Moxa C101 on IRQ%u, using %u TX + %u RX packets rings\n",
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card->irq, card->tx_ring_buffers, card->rx_ring_buffers);
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*new_card = card;
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new_card = &card->next_card;
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return 0;
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}
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static int __init c101_init(void)
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{
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if (hw == NULL) {
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#ifdef MODULE
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pr_info("no card initialized\n");
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#endif
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return -EINVAL; /* no parameters specified, abort */
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}
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pr_info("%s\n", version);
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do {
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unsigned long irq, ram;
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irq = simple_strtoul(hw, &hw, 0);
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if (*hw++ != ',')
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break;
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ram = simple_strtoul(hw, &hw, 0);
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if (*hw == ':' || *hw == '\x0')
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c101_run(irq, ram);
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if (*hw == '\x0')
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return first_card ? 0 : -EINVAL;
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}while(*hw++ == ':');
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pr_err("invalid hardware parameters\n");
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return first_card ? 0 : -EINVAL;
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}
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static void __exit c101_cleanup(void)
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{
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card_t *card = first_card;
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while (card) {
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card_t *ptr = card;
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card = card->next_card;
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unregister_hdlc_device(port_to_dev(ptr));
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c101_destroy_card(ptr);
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}
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}
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module_init(c101_init);
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module_exit(c101_cleanup);
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MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
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MODULE_DESCRIPTION("Moxa C101 serial port driver");
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MODULE_LICENSE("GPL v2");
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module_param(hw, charp, 0444);
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MODULE_PARM_DESC(hw, "irq,ram:irq,...");
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