/*
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* arch/xtensa/lib/pci-auto.c
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*
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* PCI autoconfiguration library
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*
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* Chris Zankel <zankel@tensilica.com, cez@zankel.net>
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*
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* Based on work from Matt Porter <mporter@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/pci-bridge.h>
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/*
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*
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* Setting up a PCI
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*
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* pci_ctrl->first_busno = <first bus number (0)>
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* pci_ctrl->last_busno = <last bus number (0xff)>
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* pci_ctrl->ops = <PCI config operations>
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* pci_ctrl->map_irq = <function to return the interrupt number for a device>
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*
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* pci_ctrl->io_space.start = <IO space start address (PCI view)>
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* pci_ctrl->io_space.end = <IO space end address (PCI view)>
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* pci_ctrl->io_space.base = <IO space offset: address 0 from CPU space>
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* pci_ctrl->mem_space.start = <MEM space start address (PCI view)>
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* pci_ctrl->mem_space.end = <MEM space end address (PCI view)>
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* pci_ctrl->mem_space.base = <MEM space offset: address 0 from CPU space>
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*
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* pcibios_init_resource(&pci_ctrl->io_resource, <IO space start>,
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* <IO space end>, IORESOURCE_IO, "PCI host bridge");
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* pcibios_init_resource(&pci_ctrl->mem_resources[0], <MEM space start>,
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* <MEM space end>, IORESOURCE_MEM, "PCI host bridge");
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*
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* pci_ctrl->last_busno = pciauto_bus_scan(pci_ctrl,pci_ctrl->first_busno);
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*
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* int __init pciauto_bus_scan(struct pci_controller *pci_ctrl, int current_bus)
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*
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*/
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static int pciauto_upper_iospc;
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static int pciauto_upper_memspc;
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static struct pci_dev pciauto_dev;
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static struct pci_bus pciauto_bus;
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/*
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* Helper functions
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*/
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/* Initialize the bars of a PCI device. */
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static void __init
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pciauto_setup_bars(struct pci_dev *dev, int bar_limit)
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{
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int bar_size;
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int bar, bar_nr;
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int *upper_limit;
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int found_mem64 = 0;
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for (bar = PCI_BASE_ADDRESS_0, bar_nr = 0;
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bar <= bar_limit;
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bar+=4, bar_nr++)
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{
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/* Tickle the BAR and get the size */
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pci_write_config_dword(dev, bar, 0xffffffff);
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pci_read_config_dword(dev, bar, &bar_size);
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/* If BAR is not implemented go to the next BAR */
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if (!bar_size)
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continue;
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/* Check the BAR type and set our address mask */
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if (bar_size & PCI_BASE_ADDRESS_SPACE_IO)
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{
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bar_size &= PCI_BASE_ADDRESS_IO_MASK;
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upper_limit = &pciauto_upper_iospc;
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pr_debug("PCI Autoconfig: BAR %d, I/O, ", bar_nr);
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}
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else
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{
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if ((bar_size & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64)
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found_mem64 = 1;
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bar_size &= PCI_BASE_ADDRESS_MEM_MASK;
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upper_limit = &pciauto_upper_memspc;
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pr_debug("PCI Autoconfig: BAR %d, Mem, ", bar_nr);
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}
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/* Allocate a base address (bar_size is negative!) */
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*upper_limit = (*upper_limit + bar_size) & bar_size;
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/* Write it out and update our limit */
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pci_write_config_dword(dev, bar, *upper_limit);
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/*
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* If we are a 64-bit decoder then increment to the
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* upper 32 bits of the bar and force it to locate
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* in the lower 4GB of memory.
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*/
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if (found_mem64)
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pci_write_config_dword(dev, (bar+=4), 0x00000000);
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pr_debug("size=0x%x, address=0x%x\n",
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~bar_size + 1, *upper_limit);
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}
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}
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/* Initialize the interrupt number. */
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static void __init
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pciauto_setup_irq(struct pci_controller* pci_ctrl,struct pci_dev *dev,int devfn)
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{
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u8 pin;
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int irq = 0;
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pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
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/* Fix illegal pin numbers. */
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if (pin == 0 || pin > 4)
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pin = 1;
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if (pci_ctrl->map_irq)
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irq = pci_ctrl->map_irq(dev, PCI_SLOT(devfn), pin);
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if (irq == -1)
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irq = 0;
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pr_debug("PCI Autoconfig: Interrupt %d, pin %d\n", irq, pin);
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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static void __init
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pciauto_prescan_setup_bridge(struct pci_dev *dev, int current_bus,
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int sub_bus, int *iosave, int *memsave)
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{
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/* Configure bus number registers */
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pci_write_config_byte(dev, PCI_PRIMARY_BUS, current_bus);
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pci_write_config_byte(dev, PCI_SECONDARY_BUS, sub_bus + 1);
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pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, 0xff);
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/* Round memory allocator to 1MB boundary */
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pciauto_upper_memspc &= ~(0x100000 - 1);
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*memsave = pciauto_upper_memspc;
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/* Round I/O allocator to 4KB boundary */
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pciauto_upper_iospc &= ~(0x1000 - 1);
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*iosave = pciauto_upper_iospc;
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/* Set up memory and I/O filter limits, assume 32-bit I/O space */
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pci_write_config_word(dev, PCI_MEMORY_LIMIT,
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((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
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pci_write_config_byte(dev, PCI_IO_LIMIT,
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((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
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pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
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((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
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}
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static void __init
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pciauto_postscan_setup_bridge(struct pci_dev *dev, int current_bus, int sub_bus,
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int *iosave, int *memsave)
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{
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int cmdstat;
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/* Configure bus number registers */
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pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, sub_bus);
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/*
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* Round memory allocator to 1MB boundary.
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* If no space used, allocate minimum.
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*/
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pciauto_upper_memspc &= ~(0x100000 - 1);
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if (*memsave == pciauto_upper_memspc)
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pciauto_upper_memspc -= 0x00100000;
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pci_write_config_word(dev, PCI_MEMORY_BASE, pciauto_upper_memspc >> 16);
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/* Allocate 1MB for pre-fretch */
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pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT,
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((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
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pciauto_upper_memspc -= 0x100000;
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pci_write_config_word(dev, PCI_PREF_MEMORY_BASE,
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pciauto_upper_memspc >> 16);
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/* Round I/O allocator to 4KB boundary */
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pciauto_upper_iospc &= ~(0x1000 - 1);
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if (*iosave == pciauto_upper_iospc)
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pciauto_upper_iospc -= 0x1000;
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pci_write_config_byte(dev, PCI_IO_BASE,
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(pciauto_upper_iospc & 0x0000f000) >> 8);
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pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
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pciauto_upper_iospc >> 16);
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/* Enable memory and I/O accesses, enable bus master */
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pci_read_config_dword(dev, PCI_COMMAND, &cmdstat);
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pci_write_config_dword(dev, PCI_COMMAND,
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cmdstat |
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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}
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/*
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* Scan the current PCI bus.
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*/
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int __init pciauto_bus_scan(struct pci_controller *pci_ctrl, int current_bus)
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{
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int sub_bus, pci_devfn, pci_class, cmdstat, found_multi=0;
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unsigned short vid;
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unsigned char header_type;
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struct pci_dev *dev = &pciauto_dev;
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pciauto_dev.bus = &pciauto_bus;
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pciauto_dev.sysdata = pci_ctrl;
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pciauto_bus.ops = pci_ctrl->ops;
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/*
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* Fetch our I/O and memory space upper boundaries used
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* to allocated base addresses on this pci_controller.
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*/
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if (current_bus == pci_ctrl->first_busno)
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{
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pciauto_upper_iospc = pci_ctrl->io_resource.end + 1;
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pciauto_upper_memspc = pci_ctrl->mem_resources[0].end + 1;
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}
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sub_bus = current_bus;
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for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++)
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{
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/* Skip our host bridge */
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if ((current_bus == pci_ctrl->first_busno) && (pci_devfn == 0))
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continue;
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if (PCI_FUNC(pci_devfn) && !found_multi)
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continue;
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pciauto_bus.number = current_bus;
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pciauto_dev.devfn = pci_devfn;
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/* If config space read fails from this device, move on */
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if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type))
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continue;
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if (!PCI_FUNC(pci_devfn))
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found_multi = header_type & 0x80;
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pci_read_config_word(dev, PCI_VENDOR_ID, &vid);
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if (vid == 0xffff || vid == 0x0000) {
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found_multi = 0;
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continue;
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}
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pci_read_config_dword(dev, PCI_CLASS_REVISION, &pci_class);
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if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
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int iosave, memsave;
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pr_debug("PCI Autoconfig: Found P2P bridge, device %d\n",
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PCI_SLOT(pci_devfn));
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/* Allocate PCI I/O and/or memory space */
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pciauto_setup_bars(dev, PCI_BASE_ADDRESS_1);
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pciauto_prescan_setup_bridge(dev, current_bus, sub_bus,
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&iosave, &memsave);
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sub_bus = pciauto_bus_scan(pci_ctrl, sub_bus+1);
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pciauto_postscan_setup_bridge(dev, current_bus, sub_bus,
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&iosave, &memsave);
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pciauto_bus.number = current_bus;
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continue;
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}
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/*
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* Found a peripheral, enable some standard
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* settings
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*/
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pci_read_config_dword(dev, PCI_COMMAND, &cmdstat);
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pci_write_config_dword(dev, PCI_COMMAND,
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cmdstat |
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
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/* Allocate PCI I/O and/or memory space */
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pr_debug("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n",
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current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
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pciauto_setup_bars(dev, PCI_BASE_ADDRESS_5);
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pciauto_setup_irq(pci_ctrl, dev, pci_devfn);
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}
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return sub_bus;
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}
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