/*
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* S32C1I selftest.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2016 Cadence Design Systems Inc.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/traps.h>
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#if XCHAL_HAVE_S32C1I
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static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
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/*
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* Basic atomic compare-and-swap, that records PC of S32C1I for probing.
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*
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* If *v == cmp, set *v = set. Return previous *v.
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*/
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static inline int probed_compare_swap(int *v, int cmp, int set)
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{
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int tmp;
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__asm__ __volatile__(
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" movi %1, 1f\n"
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" s32i %1, %4, 0\n"
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" wsr %2, scompare1\n"
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"1: s32c1i %0, %3, 0\n"
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: "=a" (set), "=&a" (tmp)
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: "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
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: "memory"
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);
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return set;
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}
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/* Handle probed exception */
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static void __init do_probed_exception(struct pt_regs *regs,
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unsigned long exccause)
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{
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if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
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regs->pc += 3; /* skip the s32c1i instruction */
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rcw_exc = exccause;
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} else {
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do_unhandled(regs, exccause);
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}
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}
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/* Simple test of S32C1I (soc bringup assist) */
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static int __init check_s32c1i(void)
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{
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int n, cause1, cause2;
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void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
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rcw_probe_pc = 0;
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handbus = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
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do_probed_exception);
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handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
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do_probed_exception);
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handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
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do_probed_exception);
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/* First try an S32C1I that does not store: */
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rcw_exc = 0;
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rcw_word = 1;
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n = probed_compare_swap(&rcw_word, 0, 2);
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cause1 = rcw_exc;
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/* took exception? */
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if (cause1 != 0) {
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/* unclean exception? */
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if (n != 2 || rcw_word != 1)
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panic("S32C1I exception error");
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} else if (rcw_word != 1 || n != 1) {
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panic("S32C1I compare error");
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}
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/* Then an S32C1I that stores: */
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rcw_exc = 0;
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rcw_word = 0x1234567;
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n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
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cause2 = rcw_exc;
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if (cause2 != 0) {
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/* unclean exception? */
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if (n != 0xabcde || rcw_word != 0x1234567)
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panic("S32C1I exception error (b)");
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} else if (rcw_word != 0xabcde || n != 0x1234567) {
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panic("S32C1I store error");
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}
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/* Verify consistency of exceptions: */
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if (cause1 || cause2) {
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pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
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/* If emulation of S32C1I upon bus error gets implemented,
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* we can get rid of this panic for single core (not SMP)
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*/
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panic("S32C1I exceptions not currently supported");
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}
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if (cause1 != cause2)
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panic("inconsistent S32C1I exceptions");
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trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
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trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
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trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
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return 0;
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}
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#else /* XCHAL_HAVE_S32C1I */
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/* This condition should not occur with a commercially deployed processor.
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* Display reminder for early engr test or demo chips / FPGA bitstreams
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*/
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static int __init check_s32c1i(void)
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{
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pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
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return 0;
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}
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#endif /* XCHAL_HAVE_S32C1I */
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early_initcall(check_s32c1i);
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