/*
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* Copyright (C) 2016 Atmel Corporation
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* Wenyou.Yang <wenyou.yang@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/io.h>
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#include <mach/at91_pmc.h>
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#include "pmc.h"
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DECLARE_GLOBAL_DATA_PTR;
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static int main_osc_clk_enable(struct clk *clk)
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{
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struct pmc_platdata *plat = dev_get_platdata(clk->dev);
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struct at91_pmc *pmc = plat->reg_base;
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if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
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return 0;
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return -EINVAL;
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}
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static ulong main_osc_clk_get_rate(struct clk *clk)
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{
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return gd->arch.main_clk_rate_hz;
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}
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static struct clk_ops main_osc_clk_ops = {
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.enable = main_osc_clk_enable,
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.get_rate = main_osc_clk_get_rate,
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};
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static int main_osc_clk_probe(struct udevice *dev)
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{
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return at91_pmc_core_probe(dev);
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}
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static const struct udevice_id main_osc_clk_match[] = {
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{ .compatible = "atmel,at91sam9x5-clk-main" },
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{}
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};
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U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = {
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.name = "at91sam9x5-main-osc-clk",
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.id = UCLASS_CLK,
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.of_match = main_osc_clk_match,
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.probe = main_osc_clk_probe,
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.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
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.ops = &main_osc_clk_ops,
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};
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