// SPDX-License-Identifier: GPL-2.0
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/fb.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/vmalloc.h>
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#include <linux/pagemap.h>
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#include <linux/console.h>
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#ifdef CONFIG_MTRR
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#include <asm/mtrr.h>
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#endif
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#include <linux/platform_device.h>
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#include <linux/screen_info.h>
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#include <linux/sizes.h>
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#include "sm750.h"
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#include "ddk750.h"
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#include "sm750_accel.h"
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void __iomem *mmio750;
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int hw_sm750_map(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
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{
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int ret;
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ret = 0;
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sm750_dev->vidreg_start = pci_resource_start(pdev, 1);
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sm750_dev->vidreg_size = SZ_2M;
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pr_info("mmio phyAddr = %lx\n", sm750_dev->vidreg_start);
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/*
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* reserve the vidreg space of smi adaptor
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* if you do this, you need to add release region code
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* in lynxfb_remove, or memory will not be mapped again
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* successfully
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*/
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ret = pci_request_region(pdev, 1, "sm750fb");
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if (ret) {
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pr_err("Can not request PCI regions.\n");
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goto exit;
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}
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/* now map mmio and vidmem */
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sm750_dev->pvReg = ioremap(sm750_dev->vidreg_start,
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sm750_dev->vidreg_size);
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if (!sm750_dev->pvReg) {
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pr_err("mmio failed\n");
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ret = -EFAULT;
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goto exit;
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} else {
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pr_info("mmio virtual addr = %p\n", sm750_dev->pvReg);
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}
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sm750_dev->accel.dprBase = sm750_dev->pvReg + DE_BASE_ADDR_TYPE1;
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sm750_dev->accel.dpPortBase = sm750_dev->pvReg + DE_PORT_ADDR_TYPE1;
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mmio750 = sm750_dev->pvReg;
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sm750_set_chip_type(sm750_dev->devid, sm750_dev->revid);
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sm750_dev->vidmem_start = pci_resource_start(pdev, 0);
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/*
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* don't use pdev_resource[x].end - resource[x].start to
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* calculate the resource size, it's only the maximum available
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* size but not the actual size, using
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* @ddk750_get_vm_size function can be safe.
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*/
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sm750_dev->vidmem_size = ddk750_get_vm_size();
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pr_info("video memory phyAddr = %lx, size = %u bytes\n",
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sm750_dev->vidmem_start, sm750_dev->vidmem_size);
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/* reserve the vidmem space of smi adaptor */
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sm750_dev->pvMem = ioremap_wc(sm750_dev->vidmem_start,
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sm750_dev->vidmem_size);
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if (!sm750_dev->pvMem) {
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pr_err("Map video memory failed\n");
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ret = -EFAULT;
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goto exit;
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} else {
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pr_info("video memory vaddr = %p\n", sm750_dev->pvMem);
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}
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exit:
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return ret;
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}
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int hw_sm750_inithw(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
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{
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struct init_status *parm;
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parm = &sm750_dev->initParm;
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if (parm->chip_clk == 0)
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parm->chip_clk = (sm750_get_chip_type() == SM750LE) ?
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DEFAULT_SM750LE_CHIP_CLOCK :
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DEFAULT_SM750_CHIP_CLOCK;
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if (parm->mem_clk == 0)
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parm->mem_clk = parm->chip_clk;
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if (parm->master_clk == 0)
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parm->master_clk = parm->chip_clk / 3;
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ddk750_init_hw((struct initchip_param *)&sm750_dev->initParm);
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/* for sm718, open pci burst */
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if (sm750_dev->devid == 0x718) {
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poke32(SYSTEM_CTRL,
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peek32(SYSTEM_CTRL) | SYSTEM_CTRL_PCI_BURST);
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}
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if (sm750_get_chip_type() != SM750LE) {
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unsigned int val;
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/* does user need CRT? */
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if (sm750_dev->nocrt) {
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poke32(MISC_CTRL,
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peek32(MISC_CTRL) | MISC_CTRL_DAC_POWER_OFF);
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/* shut off dpms */
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val = peek32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;
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val |= SYSTEM_CTRL_DPMS_VPHN;
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poke32(SYSTEM_CTRL, val);
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} else {
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poke32(MISC_CTRL,
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peek32(MISC_CTRL) & ~MISC_CTRL_DAC_POWER_OFF);
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/* turn on dpms */
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val = peek32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;
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val |= SYSTEM_CTRL_DPMS_VPHP;
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poke32(SYSTEM_CTRL, val);
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}
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val = peek32(PANEL_DISPLAY_CTRL) &
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~(PANEL_DISPLAY_CTRL_DUAL_DISPLAY |
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PANEL_DISPLAY_CTRL_DOUBLE_PIXEL);
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switch (sm750_dev->pnltype) {
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case sm750_24TFT:
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break;
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case sm750_doubleTFT:
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val |= PANEL_DISPLAY_CTRL_DOUBLE_PIXEL;
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break;
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case sm750_dualTFT:
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val |= PANEL_DISPLAY_CTRL_DUAL_DISPLAY;
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break;
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}
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poke32(PANEL_DISPLAY_CTRL, val);
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} else {
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/*
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* for 750LE, no DVI chip initialization
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* makes Monitor no signal
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*
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* Set up GPIO for software I2C to program DVI chip in the
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* Xilinx SP605 board, in order to have video signal.
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*/
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sm750_sw_i2c_init(0, 1);
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/*
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* Customer may NOT use CH7301 DVI chip, which has to be
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* initialized differently.
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*/
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if (sm750_sw_i2c_read_reg(0xec, 0x4a) == 0x95) {
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/*
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* The following register values for CH7301 are from
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* Chrontel app note and our experiment.
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*/
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pr_info("yes,CH7301 DVI chip found\n");
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sm750_sw_i2c_write_reg(0xec, 0x1d, 0x16);
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sm750_sw_i2c_write_reg(0xec, 0x21, 0x9);
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sm750_sw_i2c_write_reg(0xec, 0x49, 0xC0);
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pr_info("okay,CH7301 DVI chip setup done\n");
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}
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}
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/* init 2d engine */
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if (!sm750_dev->accel_off)
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hw_sm750_initAccel(sm750_dev);
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return 0;
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}
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int hw_sm750_output_setMode(struct lynxfb_output *output,
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struct fb_var_screeninfo *var,
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struct fb_fix_screeninfo *fix)
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{
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int ret;
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enum disp_output disp_set;
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int channel;
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ret = 0;
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disp_set = 0;
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channel = *output->channel;
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if (sm750_get_chip_type() != SM750LE) {
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if (channel == sm750_primary) {
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pr_info("primary channel\n");
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if (output->paths & sm750_panel)
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disp_set |= do_LCD1_PRI;
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if (output->paths & sm750_crt)
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disp_set |= do_CRT_PRI;
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} else {
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pr_info("secondary channel\n");
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if (output->paths & sm750_panel)
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disp_set |= do_LCD1_SEC;
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if (output->paths & sm750_crt)
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disp_set |= do_CRT_SEC;
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}
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ddk750_set_logical_disp_out(disp_set);
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} else {
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/* just open DISPLAY_CONTROL_750LE register bit 3:0 */
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u32 reg;
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reg = peek32(DISPLAY_CONTROL_750LE);
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reg |= 0xf;
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poke32(DISPLAY_CONTROL_750LE, reg);
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}
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pr_info("ddk setlogicdispout done\n");
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return ret;
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}
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int hw_sm750_crtc_checkMode(struct lynxfb_crtc *crtc,
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struct fb_var_screeninfo *var)
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{
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struct sm750_dev *sm750_dev;
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struct lynxfb_par *par = container_of(crtc, struct lynxfb_par, crtc);
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sm750_dev = par->dev;
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switch (var->bits_per_pixel) {
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case 8:
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case 16:
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break;
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case 32:
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if (sm750_dev->revid == SM750LE_REVISION_ID) {
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pr_debug("750le do not support 32bpp\n");
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/* set the controller's mode for @crtc charged with @var and @fix parameters */
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int hw_sm750_crtc_setMode(struct lynxfb_crtc *crtc,
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struct fb_var_screeninfo *var,
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struct fb_fix_screeninfo *fix)
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{
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int ret, fmt;
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u32 reg;
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struct mode_parameter modparm;
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enum clock_type clock;
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struct sm750_dev *sm750_dev;
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struct lynxfb_par *par;
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ret = 0;
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par = container_of(crtc, struct lynxfb_par, crtc);
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sm750_dev = par->dev;
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if (!sm750_dev->accel_off) {
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/* set 2d engine pixel format according to mode bpp */
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switch (var->bits_per_pixel) {
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case 8:
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fmt = 0;
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break;
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case 16:
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fmt = 1;
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break;
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case 32:
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default:
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fmt = 2;
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break;
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}
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sm750_hw_set2dformat(&sm750_dev->accel, fmt);
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}
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/* set timing */
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modparm.pixel_clock = ps_to_hz(var->pixclock);
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modparm.vertical_sync_polarity = (var->sync & FB_SYNC_HOR_HIGH_ACT)
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? POS : NEG;
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modparm.horizontal_sync_polarity = (var->sync & FB_SYNC_VERT_HIGH_ACT)
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? POS : NEG;
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modparm.clock_phase_polarity = (var->sync & FB_SYNC_COMP_HIGH_ACT)
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? POS : NEG;
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modparm.horizontal_display_end = var->xres;
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modparm.horizontal_sync_width = var->hsync_len;
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modparm.horizontal_sync_start = var->xres + var->right_margin;
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modparm.horizontal_total = var->xres + var->left_margin +
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var->right_margin + var->hsync_len;
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modparm.vertical_display_end = var->yres;
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modparm.vertical_sync_height = var->vsync_len;
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modparm.vertical_sync_start = var->yres + var->lower_margin;
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modparm.vertical_total = var->yres + var->upper_margin +
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var->lower_margin + var->vsync_len;
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/* choose pll */
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if (crtc->channel != sm750_secondary)
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clock = PRIMARY_PLL;
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else
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clock = SECONDARY_PLL;
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pr_debug("Request pixel clock = %lu\n", modparm.pixel_clock);
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ret = ddk750_setModeTiming(&modparm, clock);
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if (ret) {
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pr_err("Set mode timing failed\n");
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goto exit;
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}
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if (crtc->channel != sm750_secondary) {
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/* set pitch, offset, width, start address, etc... */
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poke32(PANEL_FB_ADDRESS,
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crtc->oScreen & PANEL_FB_ADDRESS_ADDRESS_MASK);
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reg = var->xres * (var->bits_per_pixel >> 3);
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/*
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* crtc->channel is not equal to par->index on numeric,
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* be aware of that
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*/
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reg = ALIGN(reg, crtc->line_pad);
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reg = (reg << PANEL_FB_WIDTH_WIDTH_SHIFT) &
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PANEL_FB_WIDTH_WIDTH_MASK;
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reg |= (fix->line_length & PANEL_FB_WIDTH_OFFSET_MASK);
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poke32(PANEL_FB_WIDTH, reg);
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reg = ((var->xres - 1) << PANEL_WINDOW_WIDTH_WIDTH_SHIFT) &
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PANEL_WINDOW_WIDTH_WIDTH_MASK;
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reg |= (var->xoffset & PANEL_WINDOW_WIDTH_X_MASK);
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poke32(PANEL_WINDOW_WIDTH, reg);
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reg = (var->yres_virtual - 1) <<
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PANEL_WINDOW_HEIGHT_HEIGHT_SHIFT;
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reg &= PANEL_WINDOW_HEIGHT_HEIGHT_MASK;
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reg |= (var->yoffset & PANEL_WINDOW_HEIGHT_Y_MASK);
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poke32(PANEL_WINDOW_HEIGHT, reg);
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poke32(PANEL_PLANE_TL, 0);
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reg = ((var->yres - 1) << PANEL_PLANE_BR_BOTTOM_SHIFT) &
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PANEL_PLANE_BR_BOTTOM_MASK;
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reg |= ((var->xres - 1) & PANEL_PLANE_BR_RIGHT_MASK);
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poke32(PANEL_PLANE_BR, reg);
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/* set pixel format */
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reg = peek32(PANEL_DISPLAY_CTRL);
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poke32(PANEL_DISPLAY_CTRL, reg | (var->bits_per_pixel >> 4));
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} else {
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/* not implemented now */
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poke32(CRT_FB_ADDRESS, crtc->oScreen);
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reg = var->xres * (var->bits_per_pixel >> 3);
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/*
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* crtc->channel is not equal to par->index on numeric,
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* be aware of that
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*/
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reg = ALIGN(reg, crtc->line_pad) << CRT_FB_WIDTH_WIDTH_SHIFT;
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reg &= CRT_FB_WIDTH_WIDTH_MASK;
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reg |= (fix->line_length & CRT_FB_WIDTH_OFFSET_MASK);
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poke32(CRT_FB_WIDTH, reg);
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/* SET PIXEL FORMAT */
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reg = peek32(CRT_DISPLAY_CTRL);
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reg |= ((var->bits_per_pixel >> 4) &
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CRT_DISPLAY_CTRL_FORMAT_MASK);
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poke32(CRT_DISPLAY_CTRL, reg);
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}
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exit:
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return ret;
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}
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int hw_sm750_setColReg(struct lynxfb_crtc *crtc, ushort index,
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ushort red, ushort green, ushort blue)
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{
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static unsigned int add[] = {PANEL_PALETTE_RAM, CRT_PALETTE_RAM};
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poke32(add[crtc->channel] + index * 4,
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(red << 16) | (green << 8) | blue);
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return 0;
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}
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int hw_sm750le_setBLANK(struct lynxfb_output *output, int blank)
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{
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int dpms, crtdb;
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switch (blank) {
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case FB_BLANK_UNBLANK:
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dpms = CRT_DISPLAY_CTRL_DPMS_0;
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crtdb = 0;
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break;
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case FB_BLANK_NORMAL:
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dpms = CRT_DISPLAY_CTRL_DPMS_0;
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crtdb = CRT_DISPLAY_CTRL_BLANK;
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break;
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case FB_BLANK_VSYNC_SUSPEND:
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dpms = CRT_DISPLAY_CTRL_DPMS_2;
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crtdb = CRT_DISPLAY_CTRL_BLANK;
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break;
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case FB_BLANK_HSYNC_SUSPEND:
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dpms = CRT_DISPLAY_CTRL_DPMS_1;
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crtdb = CRT_DISPLAY_CTRL_BLANK;
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break;
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case FB_BLANK_POWERDOWN:
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dpms = CRT_DISPLAY_CTRL_DPMS_3;
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crtdb = CRT_DISPLAY_CTRL_BLANK;
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break;
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default:
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return -EINVAL;
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}
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if (output->paths & sm750_crt) {
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unsigned int val;
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val = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_DPMS_MASK;
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poke32(CRT_DISPLAY_CTRL, val | dpms);
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val = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK;
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poke32(CRT_DISPLAY_CTRL, val | crtdb);
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}
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return 0;
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}
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int hw_sm750_setBLANK(struct lynxfb_output *output, int blank)
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{
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unsigned int dpms, pps, crtdb;
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dpms = 0;
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pps = 0;
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crtdb = 0;
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switch (blank) {
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case FB_BLANK_UNBLANK:
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pr_debug("flag = FB_BLANK_UNBLANK\n");
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dpms = SYSTEM_CTRL_DPMS_VPHP;
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pps = PANEL_DISPLAY_CTRL_DATA;
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break;
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case FB_BLANK_NORMAL:
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pr_debug("flag = FB_BLANK_NORMAL\n");
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dpms = SYSTEM_CTRL_DPMS_VPHP;
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crtdb = CRT_DISPLAY_CTRL_BLANK;
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break;
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case FB_BLANK_VSYNC_SUSPEND:
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dpms = SYSTEM_CTRL_DPMS_VNHP;
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crtdb = CRT_DISPLAY_CTRL_BLANK;
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break;
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case FB_BLANK_HSYNC_SUSPEND:
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dpms = SYSTEM_CTRL_DPMS_VPHN;
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crtdb = CRT_DISPLAY_CTRL_BLANK;
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break;
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case FB_BLANK_POWERDOWN:
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dpms = SYSTEM_CTRL_DPMS_VNHN;
|
crtdb = CRT_DISPLAY_CTRL_BLANK;
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break;
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}
|
|
if (output->paths & sm750_crt) {
|
unsigned int val = peek32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;
|
|
poke32(SYSTEM_CTRL, val | dpms);
|
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val = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK;
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poke32(CRT_DISPLAY_CTRL, val | crtdb);
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}
|
|
if (output->paths & sm750_panel) {
|
unsigned int val = peek32(PANEL_DISPLAY_CTRL);
|
|
val &= ~PANEL_DISPLAY_CTRL_DATA;
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val |= pps;
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poke32(PANEL_DISPLAY_CTRL, val);
|
}
|
|
return 0;
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}
|
|
void hw_sm750_initAccel(struct sm750_dev *sm750_dev)
|
{
|
u32 reg;
|
|
sm750_enable_2d_engine(1);
|
|
if (sm750_get_chip_type() == SM750LE) {
|
reg = peek32(DE_STATE1);
|
reg |= DE_STATE1_DE_ABORT;
|
poke32(DE_STATE1, reg);
|
|
reg = peek32(DE_STATE1);
|
reg &= ~DE_STATE1_DE_ABORT;
|
poke32(DE_STATE1, reg);
|
|
} else {
|
/* engine reset */
|
reg = peek32(SYSTEM_CTRL);
|
reg |= SYSTEM_CTRL_DE_ABORT;
|
poke32(SYSTEM_CTRL, reg);
|
|
reg = peek32(SYSTEM_CTRL);
|
reg &= ~SYSTEM_CTRL_DE_ABORT;
|
poke32(SYSTEM_CTRL, reg);
|
}
|
|
/* call 2d init */
|
sm750_dev->accel.de_init(&sm750_dev->accel);
|
}
|
|
int hw_sm750le_deWait(void)
|
{
|
int i = 0x10000000;
|
unsigned int mask = DE_STATE2_DE_STATUS_BUSY | DE_STATE2_DE_FIFO_EMPTY |
|
DE_STATE2_DE_MEM_FIFO_EMPTY;
|
|
while (i--) {
|
unsigned int val = peek32(DE_STATE2);
|
|
if ((val & mask) ==
|
(DE_STATE2_DE_FIFO_EMPTY | DE_STATE2_DE_MEM_FIFO_EMPTY))
|
return 0;
|
}
|
/* timeout error */
|
return -1;
|
}
|
|
int hw_sm750_deWait(void)
|
{
|
int i = 0x10000000;
|
unsigned int mask = SYSTEM_CTRL_DE_STATUS_BUSY |
|
SYSTEM_CTRL_DE_FIFO_EMPTY |
|
SYSTEM_CTRL_DE_MEM_FIFO_EMPTY;
|
|
while (i--) {
|
unsigned int val = peek32(SYSTEM_CTRL);
|
|
if ((val & mask) ==
|
(SYSTEM_CTRL_DE_FIFO_EMPTY | SYSTEM_CTRL_DE_MEM_FIFO_EMPTY))
|
return 0;
|
}
|
/* timeout error */
|
return -1;
|
}
|
|
int hw_sm750_pan_display(struct lynxfb_crtc *crtc,
|
const struct fb_var_screeninfo *var,
|
const struct fb_info *info)
|
{
|
u32 total;
|
/* check params */
|
if ((var->xoffset + var->xres > var->xres_virtual) ||
|
(var->yoffset + var->yres > var->yres_virtual)) {
|
return -EINVAL;
|
}
|
|
total = var->yoffset * info->fix.line_length +
|
((var->xoffset * var->bits_per_pixel) >> 3);
|
total += crtc->oScreen;
|
if (crtc->channel == sm750_primary) {
|
poke32(PANEL_FB_ADDRESS,
|
peek32(PANEL_FB_ADDRESS) |
|
(total & PANEL_FB_ADDRESS_ADDRESS_MASK));
|
} else {
|
poke32(CRT_FB_ADDRESS,
|
peek32(CRT_FB_ADDRESS) |
|
(total & CRT_FB_ADDRESS_ADDRESS_MASK));
|
}
|
return 0;
|
}
|
