/* SPDX-License-Identifier: GPL-2.0-only */
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/* Atlantic Network Driver
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef HW_ATL2_LLH_INTERNAL_H
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#define HW_ATL2_LLH_INTERNAL_H
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/* RX pif_rpf_redir_2_en_i Bitfield Definitions
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* PORT="pif_rpf_redir_2_en_i"
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*/
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#define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_ADR 0x000054C8
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#define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSK 0x00001000
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#define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSKN 0xFFFFEFFF
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#define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_SHIFT 12
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#define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_WIDTH 1
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#define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_DEFAULT 0x0
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/* RX pif_rpf_rss_hash_type_i Bitfield Definitions
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*/
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#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_ADR 0x000054C8
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#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSK 0x000001FF
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#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSKN 0xFFFFFE00
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#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_SHIFT 0
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#define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_WIDTH 9
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/* rx rpf_new_rpf_en bitfield definitions
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* preprocessor definitions for the bitfield "rpf_new_rpf_en_i".
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* port="pif_rpf_new_rpf_en_i
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*/
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/* register address for bitfield rpf_new_rpf_en */
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#define HW_ATL2_RPF_NEW_EN_ADR 0x00005104
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/* bitmask for bitfield rpf_new_rpf_en */
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#define HW_ATL2_RPF_NEW_EN_MSK 0x00000800
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/* inverted bitmask for bitfield rpf_new_rpf_en */
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#define HW_ATL2_RPF_NEW_EN_MSKN 0xfffff7ff
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/* lower bit position of bitfield rpf_new_rpf_en */
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#define HW_ATL2_RPF_NEW_EN_SHIFT 11
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/* width of bitfield rpf_new_rpf_en */
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#define HW_ATL2_RPF_NEW_EN_WIDTH 1
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/* default value of bitfield rpf_new_rpf_en */
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#define HW_ATL2_RPF_NEW_EN_DEFAULT 0x0
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/* rx l2_uc_req_tag0{f}[5:0] bitfield definitions
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* preprocessor definitions for the bitfield "l2_uc_req_tag0{f}[7:0]".
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* parameter: filter {f} | stride size 0x8 | range [0, 37]
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* port="pif_rpf_l2_uc_req_tag0[5:0]"
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*/
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/* register address for bitfield l2_uc_req_tag0{f}[2:0] */
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#define HW_ATL2_RPFL2UC_TAG_ADR(filter) (0x00005114 + (filter) * 0x8)
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/* bitmask for bitfield l2_uc_req_tag0{f}[2:0] */
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#define HW_ATL2_RPFL2UC_TAG_MSK 0x0FC00000
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/* inverted bitmask for bitfield l2_uc_req_tag0{f}[2:0] */
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#define HW_ATL2_RPFL2UC_TAG_MSKN 0xF03FFFFF
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/* lower bit position of bitfield l2_uc_req_tag0{f}[2:0] */
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#define HW_ATL2_RPFL2UC_TAG_SHIFT 22
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/* width of bitfield l2_uc_req_tag0{f}[2:0] */
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#define HW_ATL2_RPFL2UC_TAG_WIDTH 6
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/* default value of bitfield l2_uc_req_tag0{f}[2:0] */
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#define HW_ATL2_RPFL2UC_TAG_DEFAULT 0x0
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/* rpf_l2_bc_req_tag[5:0] bitfield definitions
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* preprocessor definitions for the bitfield "rpf_l2_bc_req_tag[5:0]".
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* port="pifrpf_l2_bc_req_tag_i[5:0]"
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*/
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/* register address for bitfield rpf_l2_bc_req_tag */
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#define HW_ATL2_RPF_L2_BC_TAG_ADR 0x000050F0
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/* bitmask for bitfield rpf_l2_bc_req_tag */
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#define HW_ATL2_RPF_L2_BC_TAG_MSK 0x0000003F
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/* inverted bitmask for bitfield rpf_l2_bc_req_tag */
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#define HW_ATL2_RPF_L2_BC_TAG_MSKN 0xffffffc0
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/* lower bit position of bitfield rpf_l2_bc_req_tag */
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#define HW_ATL2_RPF_L2_BC_TAG_SHIFT 0
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/* width of bitfield rpf_l2_bc_req_tag */
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#define HW_ATL2_RPF_L2_BC_TAG_WIDTH 6
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/* default value of bitfield rpf_l2_bc_req_tag */
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#define HW_ATL2_RPF_L2_BC_TAG_DEFAULT 0x0
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/* rx rpf_rss_red1_data_[4:0] bitfield definitions
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* preprocessor definitions for the bitfield "rpf_rss_red1_data[4:0]".
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* port="pif_rpf_rss_red1_data_i[4:0]"
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*/
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/* register address for bitfield rpf_rss_red1_data[4:0] */
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#define HW_ATL2_RPF_RSS_REDIR_ADR(TC, INDEX) (0x00006200 + \
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(0x100 * !!((TC) > 3)) + (INDEX) * 4)
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/* bitmask for bitfield rpf_rss_red1_data[4:0] */
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#define HW_ATL2_RPF_RSS_REDIR_MSK(TC) (0x00000001F << (5 * ((TC) % 4)))
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/* lower bit position of bitfield rpf_rss_red1_data[4:0] */
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#define HW_ATL2_RPF_RSS_REDIR_SHIFT(TC) (5 * ((TC) % 4))
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/* width of bitfield rpf_rss_red1_data[4:0] */
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#define HW_ATL2_RPF_RSS_REDIR_WIDTH 5
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/* default value of bitfield rpf_rss_red1_data[4:0] */
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#define HW_ATL2_RPF_RSS_REDIR_DEFAULT 0x0
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/* rx vlan_req_tag0{f}[3:0] bitfield definitions
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* preprocessor definitions for the bitfield "vlan_req_tag0{f}[3:0]".
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* parameter: filter {f} | stride size 0x4 | range [0, 15]
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* port="pif_rpf_vlan_req_tag0[3:0]"
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*/
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/* register address for bitfield vlan_req_tag0{f}[3:0] */
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#define HW_ATL2_RPF_VL_TAG_ADR(filter) (0x00005290 + (filter) * 0x4)
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/* bitmask for bitfield vlan_req_tag0{f}[3:0] */
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#define HW_ATL2_RPF_VL_TAG_MSK 0x0000F000
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/* inverted bitmask for bitfield vlan_req_tag0{f}[3:0] */
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#define HW_ATL2_RPF_VL_TAG_MSKN 0xFFFF0FFF
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/* lower bit position of bitfield vlan_req_tag0{f}[3:0] */
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#define HW_ATL2_RPF_VL_TAG_SHIFT 12
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/* width of bitfield vlan_req_tag0{f}[3:0] */
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#define HW_ATL2_RPF_VL_TAG_WIDTH 4
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/* default value of bitfield vlan_req_tag0{f}[3:0] */
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#define HW_ATL2_RPF_VL_TAG_DEFAULT 0x0
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/* RX rx_q{Q}_tc_map[2:0] Bitfield Definitions
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* Preprocessor definitions for the bitfield "rx_q{Q}_tc_map[2:0]".
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* Parameter: Queue {Q} | bit-level stride | range [0, 31]
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* PORT="pif_rx_q0_tc_map_i[2:0]"
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*/
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/* Register address for bitfield rx_q{Q}_tc_map[2:0] */
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#define HW_ATL2_RX_Q_TC_MAP_ADR(queue) \
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(((queue) < 32) ? 0x00005900 + ((queue) / 8) * 4 : 0)
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/* Lower bit position of bitfield rx_q{Q}_tc_map[2:0] */
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#define HW_ATL2_RX_Q_TC_MAP_SHIFT(queue) \
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(((queue) < 32) ? ((queue) * 4) % 32 : 0)
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/* Width of bitfield rx_q{Q}_tc_map[2:0] */
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#define HW_ATL2_RX_Q_TC_MAP_WIDTH 3
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/* Default value of bitfield rx_q{Q}_tc_map[2:0] */
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#define HW_ATL2_RX_Q_TC_MAP_DEFAULT 0x0
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/* tx tx_tc_q_rand_map_en bitfield definitions
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* preprocessor definitions for the bitfield "tx_tc_q_rand_map_en".
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* port="pif_tpb_tx_tc_q_rand_map_en_i"
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*/
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/* register address for bitfield tx_tc_q_rand_map_en */
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#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_ADR 0x00007900
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/* bitmask for bitfield tx_tc_q_rand_map_en */
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#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSK 0x00000200
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/* inverted bitmask for bitfield tx_tc_q_rand_map_en */
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#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSKN 0xFFFFFDFF
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/* lower bit position of bitfield tx_tc_q_rand_map_en */
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#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_SHIFT 9
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/* width of bitfield tx_tc_q_rand_map_en */
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#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_WIDTH 1
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/* default value of bitfield tx_tc_q_rand_map_en */
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#define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_DEFAULT 0x0
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/* tx tx_buffer_clk_gate_en bitfield definitions
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* preprocessor definitions for the bitfield "tx_buffer_clk_gate_en".
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* port="pif_tpb_tx_buffer_clk_gate_en_i"
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*/
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/* register address for bitfield tx_buffer_clk_gate_en */
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#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_ADR 0x00007900
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/* bitmask for bitfield tx_buffer_clk_gate_en */
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#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSK 0x00000020
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/* inverted bitmask for bitfield tx_buffer_clk_gate_en */
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#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSKN 0xffffffdf
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/* lower bit position of bitfield tx_buffer_clk_gate_en */
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#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_SHIFT 5
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/* width of bitfield tx_buffer_clk_gate_en */
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#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_WIDTH 1
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/* default value of bitfield tx_buffer_clk_gate_en */
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#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_DEFAULT 0x0
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/* tx tx_q_tc_map{q} bitfield definitions
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* preprocessor definitions for the bitfield "tx_q_tc_map{q}".
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* parameter: queue {q} | bit-level stride | range [0, 31]
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* port="pif_tpb_tx_q_tc_map0_i[2:0]"
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*/
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/* register address for bitfield tx_q_tc_map{q} */
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#define HW_ATL2_TX_Q_TC_MAP_ADR(queue) \
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(((queue) < 32) ? 0x0000799C + ((queue) / 4) * 4 : 0)
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/* lower bit position of bitfield tx_q_tc_map{q} */
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#define HW_ATL2_TX_Q_TC_MAP_SHIFT(queue) \
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(((queue) < 32) ? ((queue) * 8) % 32 : 0)
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/* width of bitfield tx_q_tc_map{q} */
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#define HW_ATL2_TX_Q_TC_MAP_WIDTH 3
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/* default value of bitfield tx_q_tc_map{q} */
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#define HW_ATL2_TX_Q_TC_MAP_DEFAULT 0x0
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/* tx data_tc_arb_mode bitfield definitions
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* preprocessor definitions for the bitfield "data_tc_arb_mode".
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* port="pif_tps_data_tc_arb_mode_i"
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*/
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/* register address for bitfield data_tc_arb_mode */
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#define HW_ATL2_TPS_DATA_TC_ARB_MODE_ADR 0x00007100
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/* bitmask for bitfield data_tc_arb_mode */
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#define HW_ATL2_TPS_DATA_TC_ARB_MODE_MSK 0x00000003
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/* inverted bitmask for bitfield data_tc_arb_mode */
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#define HW_ATL2_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffc
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/* lower bit position of bitfield data_tc_arb_mode */
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#define HW_ATL2_TPS_DATA_TC_ARB_MODE_SHIFT 0
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/* width of bitfield data_tc_arb_mode */
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#define HW_ATL2_TPS_DATA_TC_ARB_MODE_WIDTH 2
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/* default value of bitfield data_tc_arb_mode */
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#define HW_ATL2_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0
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/* tx data_tc{t}_credit_max[f:0] bitfield definitions
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* preprocessor definitions for the bitfield "data_tc{t}_credit_max[f:0]".
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* parameter: tc {t} | stride size 0x4 | range [0, 7]
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* port="pif_tps_data_tc0_credit_max_i[15:0]"
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*/
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/* register address for bitfield data_tc{t}_credit_max[f:0] */
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#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4)
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/* bitmask for bitfield data_tc{t}_credit_max[f:0] */
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#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK 0xffff0000
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/* inverted bitmask for bitfield data_tc{t}_credit_max[f:0] */
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#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSKN 0x0000ffff
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/* lower bit position of bitfield data_tc{t}_credit_max[f:0] */
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#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_SHIFT 16
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/* width of bitfield data_tc{t}_credit_max[f:0] */
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#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_WIDTH 16
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/* default value of bitfield data_tc{t}_credit_max[f:0] */
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#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0
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/* tx data_tc{t}_weight[e:0] bitfield definitions
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* preprocessor definitions for the bitfield "data_tc{t}_weight[e:0]".
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* parameter: tc {t} | stride size 0x4 | range [0, 7]
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* port="pif_tps_data_tc0_weight_i[14:0]"
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*/
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/* register address for bitfield data_tc{t}_weight[e:0] */
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#define HW_ATL2_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4)
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/* bitmask for bitfield data_tc{t}_weight[e:0] */
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#define HW_ATL2_TPS_DATA_TCTWEIGHT_MSK 0x00007fff
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/* inverted bitmask for bitfield data_tc{t}_weight[e:0] */
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#define HW_ATL2_TPS_DATA_TCTWEIGHT_MSKN 0xffff8000
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/* lower bit position of bitfield data_tc{t}_weight[e:0] */
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#define HW_ATL2_TPS_DATA_TCTWEIGHT_SHIFT 0
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/* width of bitfield data_tc{t}_weight[e:0] */
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#define HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH 15
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/* default value of bitfield data_tc{t}_weight[e:0] */
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#define HW_ATL2_TPS_DATA_TCTWEIGHT_DEFAULT 0x0
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/* tx interrupt moderation control register definitions
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* Preprocessor definitions for TX Interrupt Moderation Control Register
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* Base Address: 0x00007c28
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* Parameter: queue {Q} | stride size 0x4 | range [0, 31]
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*/
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#define HW_ATL2_TX_INTR_MODERATION_CTL_ADR(queue) (0x00007c28u + (queue) * 0x40)
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/* Launch time control register */
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#define HW_ATL2_LT_CTRL_ADR 0x00007a1c
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#define HW_ATL2_LT_CTRL_AVB_LEN_CMP_TRSHLD_MSK 0xFFFF0000
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#define HW_ATL2_LT_CTRL_AVB_LEN_CMP_TRSHLD_SHIFT 16
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#define HW_ATL2_LT_CTRL_CLK_RATIO_MSK 0x0000FF00
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#define HW_ATL2_LT_CTRL_CLK_RATIO_SHIFT 8
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#define HW_ATL2_LT_CTRL_CLK_RATIO_QUATER_SPEED 4
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#define HW_ATL2_LT_CTRL_CLK_RATIO_HALF_SPEED 2
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#define HW_ATL2_LT_CTRL_CLK_RATIO_FULL_SPEED 1
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#define HW_ATL2_LT_CTRL_25G_MODE_SUPPORT_MSK 0x00000008
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#define HW_ATL2_LT_CTRL_25G_MODE_SUPPORT_SHIFT 3
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#define HW_ATL2_LT_CTRL_LINK_SPEED_MSK 0x00000007
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#define HW_ATL2_LT_CTRL_LINK_SPEED_SHIFT 0
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/* FPGA VER register */
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#define HW_ATL2_FPGA_VER_ADR 0x000000f4
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#define HW_ATL2_FPGA_VER_U32(mj, mi, bl, rv) \
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((((mj) & 0xff) << 24) | \
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(((mi) & 0xff) << 16) | \
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(((bl) & 0xff) << 8) | \
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(((rv) & 0xff) << 0))
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/* ahb_mem_addr{f}[31:0] Bitfield Definitions
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* Preprocessor definitions for the bitfield "ahb_mem_addr{f}[31:0]".
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* Parameter: filter {f} | stride size 0x10 | range [0, 127]
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* PORT="ahb_mem_addr{f}[31:0]"
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*/
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/* Register address for bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_ADR(filter) \
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(0x00014000u + (filter) * 0x10)
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/* Bitmask for bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_MSK 0xFFFFFFFFu
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/* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_MSKN 0x00000000u
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/* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_SHIFT 0
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/* Width of bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_WIDTH 31
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/* Default value of bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_DEFAULT 0x0
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/* Register address for bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_ADR(filter) \
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(0x00014004u + (filter) * 0x10)
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/* Bitmask for bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_MSK 0xFFFFFFFFu
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/* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_MSKN 0x00000000u
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/* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_SHIFT 0
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/* Width of bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_WIDTH 31
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/* Default value of bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_DEFAULT 0x0
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/* Register address for bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_ACTN_ADR(filter) \
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(0x00014008u + (filter) * 0x10)
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/* Bitmask for bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_ACTN_MSK 0x000007FFu
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/* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_ACTN_MSKN 0xFFFFF800u
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/* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_ACTN_SHIFT 0
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/* Width of bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_ACTN_WIDTH 10
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/* Default value of bitfield ahb_mem_addr{f}[31:0] */
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#define HW_ATL2_RPF_ACT_RSLVR_ACTN_DEFAULT 0x0
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/* rpf_rec_tab_en[15:0] Bitfield Definitions
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* Preprocessor definitions for the bitfield "rpf_rec_tab_en[15:0]".
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* PORT="pif_rpf_rec_tab_en[15:0]"
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*/
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/* Register address for bitfield rpf_rec_tab_en[15:0] */
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#define HW_ATL2_RPF_REC_TAB_EN_ADR 0x00006ff0u
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/* Bitmask for bitfield rpf_rec_tab_en[15:0] */
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#define HW_ATL2_RPF_REC_TAB_EN_MSK 0x0000FFFFu
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/* Inverted bitmask for bitfield rpf_rec_tab_en[15:0] */
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#define HW_ATL2_RPF_REC_TAB_EN_MSKN 0xFFFF0000u
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/* Lower bit position of bitfield rpf_rec_tab_en[15:0] */
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#define HW_ATL2_RPF_REC_TAB_EN_SHIFT 0
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/* Width of bitfield rpf_rec_tab_en[15:0] */
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#define HW_ATL2_RPF_REC_TAB_EN_WIDTH 16
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/* Default value of bitfield rpf_rec_tab_en[15:0] */
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#define HW_ATL2_RPF_REC_TAB_EN_DEFAULT 0x0
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/* Register address for firmware shared input buffer */
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#define HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(dword) (0x00012000U + (dword) * 0x4U)
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/* Register address for firmware shared output buffer */
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#define HW_ATL2_MIF_SHARED_BUFFER_OUT_ADR(dword) (0x00013000U + (dword) * 0x4U)
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/* pif_host_finished_buf_wr_i Bitfield Definitions
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* Preprocessor definitions for the bitfield "pif_host_finished_buf_wr_i".
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* PORT="pif_host_finished_buf_wr_i"
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*/
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/* Register address for bitfield rpif_host_finished_buf_wr_i */
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#define HW_ATL2_MIF_HOST_FINISHED_WRITE_ADR 0x00000e00u
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/* Bitmask for bitfield pif_host_finished_buf_wr_i */
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#define HW_ATL2_MIF_HOST_FINISHED_WRITE_MSK 0x00000001u
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/* Inverted bitmask for bitfield pif_host_finished_buf_wr_i */
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#define HW_ATL2_MIF_HOST_FINISHED_WRITE_MSKN 0xFFFFFFFEu
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/* Lower bit position of bitfield pif_host_finished_buf_wr_i */
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#define HW_ATL2_MIF_HOST_FINISHED_WRITE_SHIFT 0
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/* Width of bitfield pif_host_finished_buf_wr_i */
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#define HW_ATL2_MIF_HOST_FINISHED_WRITE_WIDTH 1
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/* Default value of bitfield pif_host_finished_buf_wr_i */
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#define HW_ATL2_MIF_HOST_FINISHED_WRITE_DEFAULT 0x0
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/* pif_mcp_finished_buf_rd_i Bitfield Definitions
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* Preprocessor definitions for the bitfield "pif_mcp_finished_buf_rd_i".
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* PORT="pif_mcp_finished_buf_rd_i"
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*/
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/* Register address for bitfield pif_mcp_finished_buf_rd_i */
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#define HW_ATL2_MIF_MCP_FINISHED_READ_ADR 0x00000e04u
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/* Bitmask for bitfield pif_mcp_finished_buf_rd_i */
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#define HW_ATL2_MIF_MCP_FINISHED_READ_MSK 0x00000001u
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/* Inverted bitmask for bitfield pif_mcp_finished_buf_rd_i */
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#define HW_ATL2_MIF_MCP_FINISHED_READ_MSKN 0xFFFFFFFEu
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/* Lower bit position of bitfield pif_mcp_finished_buf_rd_i */
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#define HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT 0
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/* Width of bitfield pif_mcp_finished_buf_rd_i */
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#define HW_ATL2_MIF_MCP_FINISHED_READ_WIDTH 1
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/* Default value of bitfield pif_mcp_finished_buf_rd_i */
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#define HW_ATL2_MIF_MCP_FINISHED_READ_DEFAULT 0x0
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/* Register address for bitfield pif_mcp_boot_reg */
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#define HW_ATL2_MIF_BOOT_REG_ADR 0x00003040u
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#define HW_ATL2_MCP_HOST_REQ_INT_READY BIT(0)
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#define HW_ATL2_MCP_HOST_REQ_INT_ADR 0x00000F00u
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#define HW_ATL2_MCP_HOST_REQ_INT_SET_ADR 0x00000F04u
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#define HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR 0x00000F08u
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#endif /* HW_ATL2_LLH_INTERNAL_H */
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