// SPDX-License-Identifier: GPL-2.0-only
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/* Atlantic Network Driver
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#include "hw_atl2_llh.h"
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#include "hw_atl2_llh_internal.h"
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#include "aq_hw_utils.h"
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void hw_atl2_rpf_redirection_table2_select_set(struct aq_hw_s *aq_hw,
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u32 select)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_ADR,
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HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSK,
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HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_SHIFT, select);
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}
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void hw_atl2_rpf_rss_hash_type_set(struct aq_hw_s *aq_hw, u32 rss_hash_type)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_ADR,
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HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSK,
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HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_SHIFT,
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rss_hash_type);
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}
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/* rpf */
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void hw_atl2_rpf_new_enable_set(struct aq_hw_s *aq_hw, u32 enable)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_NEW_EN_ADR,
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HW_ATL2_RPF_NEW_EN_MSK,
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HW_ATL2_RPF_NEW_EN_SHIFT,
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enable);
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}
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void hw_atl2_rpfl2_uc_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPFL2UC_TAG_ADR(filter),
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HW_ATL2_RPFL2UC_TAG_MSK,
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HW_ATL2_RPFL2UC_TAG_SHIFT,
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tag);
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}
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void hw_atl2_rpfl2_bc_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_L2_BC_TAG_ADR,
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HW_ATL2_RPF_L2_BC_TAG_MSK,
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HW_ATL2_RPF_L2_BC_TAG_SHIFT,
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tag);
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}
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void hw_atl2_new_rpf_rss_redir_set(struct aq_hw_s *aq_hw, u32 tc, u32 index,
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u32 queue)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_RSS_REDIR_ADR(tc, index),
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HW_ATL2_RPF_RSS_REDIR_MSK(tc),
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HW_ATL2_RPF_RSS_REDIR_SHIFT(tc),
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queue);
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}
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void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_VL_TAG_ADR(filter),
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HW_ATL2_RPF_VL_TAG_MSK,
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HW_ATL2_RPF_VL_TAG_SHIFT,
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tag);
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}
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/* TX */
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void hw_atl2_tpb_tx_tc_q_rand_map_en_set(struct aq_hw_s *aq_hw,
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const u32 tc_q_rand_map_en)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_ADR,
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HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSK,
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HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_SHIFT,
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tc_q_rand_map_en);
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}
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void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gate_en)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_ADR,
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HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSK,
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HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_SHIFT,
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clk_gate_en);
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}
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void hw_atl2_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
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u32 tx_intr_moderation_ctl,
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u32 queue)
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{
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aq_hw_write_reg(aq_hw, HW_ATL2_TX_INTR_MODERATION_CTL_ADR(queue),
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tx_intr_moderation_ctl);
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}
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void hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
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const u32 data_arb_mode)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TC_ARB_MODE_ADR,
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HW_ATL2_TPS_DATA_TC_ARB_MODE_MSK,
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HW_ATL2_TPS_DATA_TC_ARB_MODE_SHIFT,
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data_arb_mode);
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}
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void hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
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const u32 tc,
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const u32 max_credit)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
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HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK,
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HW_ATL2_TPS_DATA_TCTCREDIT_MAX_SHIFT,
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max_credit);
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}
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void hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
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const u32 tc,
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const u32 weight)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TCTWEIGHT_ADR(tc),
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HW_ATL2_TPS_DATA_TCTWEIGHT_MSK,
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HW_ATL2_TPS_DATA_TCTWEIGHT_SHIFT,
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weight);
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}
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u32 hw_atl2_get_hw_version(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL2_FPGA_VER_ADR);
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}
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void hw_atl2_init_launchtime(struct aq_hw_s *aq_hw)
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{
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u32 hw_ver = hw_atl2_get_hw_version(aq_hw);
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_LT_CTRL_ADR,
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HW_ATL2_LT_CTRL_CLK_RATIO_MSK,
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HW_ATL2_LT_CTRL_CLK_RATIO_SHIFT,
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hw_ver < HW_ATL2_FPGA_VER_U32(1, 0, 0, 0) ?
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HW_ATL2_LT_CTRL_CLK_RATIO_FULL_SPEED :
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hw_ver >= HW_ATL2_FPGA_VER_U32(1, 0, 85, 2) ?
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HW_ATL2_LT_CTRL_CLK_RATIO_HALF_SPEED :
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HW_ATL2_LT_CTRL_CLK_RATIO_QUATER_SPEED);
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}
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/* set action resolver record */
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void hw_atl2_rpf_act_rslvr_record_set(struct aq_hw_s *aq_hw, u8 location,
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u32 tag, u32 mask, u32 action)
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{
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aq_hw_write_reg(aq_hw,
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HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_ADR(location),
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tag);
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aq_hw_write_reg(aq_hw,
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HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_ADR(location),
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mask);
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aq_hw_write_reg(aq_hw,
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HW_ATL2_RPF_ACT_RSLVR_ACTN_ADR(location),
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action);
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}
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void hw_atl2_rpf_act_rslvr_section_en_set(struct aq_hw_s *aq_hw, u32 sections)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_REC_TAB_EN_ADR,
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HW_ATL2_RPF_REC_TAB_EN_MSK,
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HW_ATL2_RPF_REC_TAB_EN_SHIFT,
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sections);
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}
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void hw_atl2_mif_shared_buf_get(struct aq_hw_s *aq_hw, int offset, u32 *data,
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int len)
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{
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int j = 0;
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int i;
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for (i = offset; i < offset + len; i++, j++)
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data[j] = aq_hw_read_reg(aq_hw,
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HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(i));
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}
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void hw_atl2_mif_shared_buf_write(struct aq_hw_s *aq_hw, int offset, u32 *data,
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int len)
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{
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int j = 0;
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int i;
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for (i = offset; i < offset + len; i++, j++)
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aq_hw_write_reg(aq_hw, HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(i),
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data[j]);
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}
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void hw_atl2_mif_shared_buf_read(struct aq_hw_s *aq_hw, int offset, u32 *data,
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int len)
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{
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int j = 0;
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int i;
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for (i = offset; i < offset + len; i++, j++)
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data[j] = aq_hw_read_reg(aq_hw,
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HW_ATL2_MIF_SHARED_BUFFER_OUT_ADR(i));
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}
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void hw_atl2_mif_host_finished_write_set(struct aq_hw_s *aq_hw, u32 finish)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_MIF_HOST_FINISHED_WRITE_ADR,
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HW_ATL2_MIF_HOST_FINISHED_WRITE_MSK,
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HW_ATL2_MIF_HOST_FINISHED_WRITE_SHIFT,
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finish);
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}
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u32 hw_atl2_mif_mcp_finished_read_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg_bit(aq_hw, HW_ATL2_MIF_MCP_FINISHED_READ_ADR,
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HW_ATL2_MIF_MCP_FINISHED_READ_MSK,
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HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT);
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}
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u32 hw_atl2_mif_mcp_boot_reg_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL2_MIF_BOOT_REG_ADR);
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}
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void hw_atl2_mif_mcp_boot_reg_set(struct aq_hw_s *aq_hw, u32 val)
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{
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return aq_hw_write_reg(aq_hw, HW_ATL2_MIF_BOOT_REG_ADR, val);
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}
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u32 hw_atl2_mif_host_req_int_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL2_MCP_HOST_REQ_INT_ADR);
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}
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void hw_atl2_mif_host_req_int_clr(struct aq_hw_s *aq_hw, u32 val)
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{
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return aq_hw_write_reg(aq_hw, HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR,
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val);
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}
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