// SPDX-License-Identifier: GPL-2.0-only
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/* Atlantic Network Driver
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*
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* Copyright (C) 2014-2019 aQuantia Corporation
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* Copyright (C) 2019-2020 Marvell International Ltd.
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*/
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/* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
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* Atlantic hardware abstraction layer.
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*/
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#include "../aq_hw.h"
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#include "../aq_hw_utils.h"
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#include "../aq_pci_func.h"
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#include "../aq_ring.h"
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#include "../aq_vec.h"
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#include "../aq_nic.h"
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#include "hw_atl_utils.h"
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#include "hw_atl_llh.h"
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#define HW_ATL_FW2X_MPI_LED_ADDR 0x31c
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#define HW_ATL_FW2X_MPI_RPC_ADDR 0x334
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#define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
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#define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
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#define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
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#define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
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#define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
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#define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
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#define HW_ATL_FW3X_EXT_CONTROL_ADDR 0x378
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#define HW_ATL_FW3X_EXT_STATE_ADDR 0x37c
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#define HW_ATL_FW3X_PTP_ADJ_LSW_ADDR 0x50a0
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#define HW_ATL_FW3X_PTP_ADJ_MSW_ADDR 0x50a4
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#define HW_ATL_FW2X_CAP_PAUSE BIT(CAPS_HI_PAUSE)
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#define HW_ATL_FW2X_CAP_ASYM_PAUSE BIT(CAPS_HI_ASYMMETRIC_PAUSE)
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#define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY)
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#define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL)
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#define HW_ATL_FW2X_CTRL_WAKE_ON_LINK BIT(CTRL_WAKE_ON_LINK)
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#define HW_ATL_FW2X_CTRL_SLEEP_PROXY BIT(CTRL_SLEEP_PROXY)
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#define HW_ATL_FW2X_CTRL_WOL BIT(CTRL_WOL)
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#define HW_ATL_FW2X_CTRL_LINK_DROP BIT(CTRL_LINK_DROP)
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#define HW_ATL_FW2X_CTRL_PAUSE BIT(CTRL_PAUSE)
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#define HW_ATL_FW2X_CTRL_TEMPERATURE BIT(CTRL_TEMPERATURE)
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#define HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE BIT(CTRL_ASYMMETRIC_PAUSE)
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#define HW_ATL_FW2X_CTRL_INT_LOOPBACK BIT(CTRL_INT_LOOPBACK)
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#define HW_ATL_FW2X_CTRL_EXT_LOOPBACK BIT(CTRL_EXT_LOOPBACK)
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#define HW_ATL_FW2X_CTRL_DOWNSHIFT BIT(CTRL_DOWNSHIFT)
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#define HW_ATL_FW2X_CTRL_FORCE_RECONNECT BIT(CTRL_FORCE_RECONNECT)
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#define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE)
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#define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE)
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#define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE)
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#define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE)
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#define HW_ATL_FW2X_CAP_MACSEC BIT(CAPS_LO_MACSEC)
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#define HAL_ATLANTIC_WOL_FILTERS_COUNT 8
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#define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E
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#define HW_ATL_FW_VER_LED 0x03010026U
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#define HW_ATL_FW_VER_MEDIA_CONTROL 0x0301005aU
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struct __packed fw2x_msg_wol_pattern {
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u8 mask[16];
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u32 crc;
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};
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struct __packed fw2x_msg_wol {
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u32 msg_id;
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u8 hw_addr[ETH_ALEN];
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u8 magic_packet_enabled;
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u8 filter_count;
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struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT];
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u8 link_up_enabled;
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u8 link_down_enabled;
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u16 reserved;
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u32 link_up_timeout;
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u32 link_down_timeout;
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};
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static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
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static int aq_fw2x_set_state(struct aq_hw_s *self,
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enum hal_atl_utils_fw_state_e state);
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static u32 aq_fw2x_mbox_get(struct aq_hw_s *self);
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static u32 aq_fw2x_rpc_get(struct aq_hw_s *self);
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static int aq_fw2x_settings_get(struct aq_hw_s *self, u32 *addr);
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static u32 aq_fw2x_state_get(struct aq_hw_s *self);
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static u32 aq_fw2x_state2_get(struct aq_hw_s *self);
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static int aq_fw2x_init(struct aq_hw_s *self)
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{
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int err = 0;
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/* check 10 times by 1ms */
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err = readx_poll_timeout_atomic(aq_fw2x_mbox_get,
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self, self->mbox_addr,
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self->mbox_addr != 0U,
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1000U, 10000U);
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err = readx_poll_timeout_atomic(aq_fw2x_rpc_get,
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self, self->rpc_addr,
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self->rpc_addr != 0U,
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1000U, 100000U);
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err = aq_fw2x_settings_get(self, &self->settings_addr);
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return err;
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}
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static int aq_fw2x_deinit(struct aq_hw_s *self)
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{
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int err = aq_fw2x_set_link_speed(self, 0);
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if (!err)
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err = aq_fw2x_set_state(self, MPI_DEINIT);
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return err;
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}
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static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
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{
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enum hw_atl_fw2x_rate rate = 0;
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if (speed & AQ_NIC_RATE_10G)
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rate |= FW2X_RATE_10G;
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if (speed & AQ_NIC_RATE_5G)
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rate |= FW2X_RATE_5G;
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if (speed & AQ_NIC_RATE_2G5)
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rate |= FW2X_RATE_2G5;
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if (speed & AQ_NIC_RATE_1G)
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rate |= FW2X_RATE_1G;
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if (speed & AQ_NIC_RATE_100M)
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rate |= FW2X_RATE_100M;
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return rate;
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}
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static u32 fw2x_to_eee_mask(u32 speed)
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{
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u32 rate = 0;
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if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK)
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rate |= AQ_NIC_RATE_EEE_10G;
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if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK)
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rate |= AQ_NIC_RATE_EEE_5G;
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if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK)
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rate |= AQ_NIC_RATE_EEE_2G5;
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if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK)
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rate |= AQ_NIC_RATE_EEE_1G;
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return rate;
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}
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static u32 eee_mask_to_fw2x(u32 speed)
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{
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u32 rate = 0;
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if (speed & AQ_NIC_RATE_EEE_10G)
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rate |= HW_ATL_FW2X_CAP_EEE_10G_MASK;
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if (speed & AQ_NIC_RATE_EEE_5G)
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rate |= HW_ATL_FW2X_CAP_EEE_5G_MASK;
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if (speed & AQ_NIC_RATE_EEE_2G5)
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rate |= HW_ATL_FW2X_CAP_EEE_2G5_MASK;
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if (speed & AQ_NIC_RATE_EEE_1G)
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rate |= HW_ATL_FW2X_CAP_EEE_1G_MASK;
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return rate;
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}
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static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
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{
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u32 val = link_speed_mask_2fw2x_ratemask(speed);
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
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return 0;
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}
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static void aq_fw2x_upd_flow_control_bits(struct aq_hw_s *self,
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u32 *mpi_state, u32 fc)
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{
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*mpi_state &= ~(HW_ATL_FW2X_CTRL_PAUSE |
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HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE);
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switch (fc) {
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/* There is not explicit mode of RX only pause frames,
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* thus, we join this mode with FC full.
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* FC full is either Rx, either Tx, or both.
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*/
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case AQ_NIC_FC_FULL:
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case AQ_NIC_FC_RX:
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*mpi_state |= HW_ATL_FW2X_CTRL_PAUSE |
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HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE;
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break;
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case AQ_NIC_FC_TX:
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*mpi_state |= HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE;
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break;
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}
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}
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static void aq_fw2x_upd_eee_rate_bits(struct aq_hw_s *self, u32 *mpi_opts,
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u32 eee_speeds)
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{
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*mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK |
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HW_ATL_FW2X_CAP_EEE_2G5_MASK |
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HW_ATL_FW2X_CAP_EEE_5G_MASK |
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HW_ATL_FW2X_CAP_EEE_10G_MASK);
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*mpi_opts |= eee_mask_to_fw2x(eee_speeds);
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}
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static int aq_fw2x_set_state(struct aq_hw_s *self,
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enum hal_atl_utils_fw_state_e state)
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{
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u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
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struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
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switch (state) {
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case MPI_INIT:
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mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
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aq_fw2x_upd_eee_rate_bits(self, &mpi_state, cfg->eee_speeds);
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aq_fw2x_upd_flow_control_bits(self, &mpi_state,
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self->aq_nic_cfg->fc.req);
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break;
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case MPI_DEINIT:
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mpi_state |= BIT(CAPS_HI_LINK_DROP);
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break;
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case MPI_RESET:
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case MPI_POWER:
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/* No actions */
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break;
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}
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
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return 0;
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}
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static int aq_fw2x_update_link_status(struct aq_hw_s *self)
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{
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struct aq_hw_link_status_s *link_status = &self->aq_link_status;
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u32 mpi_state;
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u32 speed;
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mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
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speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
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FW2X_RATE_2G5 | FW2X_RATE_5G |
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FW2X_RATE_10G);
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if (speed) {
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if (speed & FW2X_RATE_10G)
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link_status->mbps = 10000;
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else if (speed & FW2X_RATE_5G)
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link_status->mbps = 5000;
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else if (speed & FW2X_RATE_2G5)
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link_status->mbps = 2500;
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else if (speed & FW2X_RATE_1G)
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link_status->mbps = 1000;
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else if (speed & FW2X_RATE_100M)
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link_status->mbps = 100;
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else
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link_status->mbps = 10000;
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} else {
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link_status->mbps = 0;
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}
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link_status->full_duplex = true;
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return 0;
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}
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static int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
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{
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u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
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u32 mac_addr[2] = { 0 };
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int err = 0;
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if (efuse_addr != 0) {
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err = hw_atl_utils_fw_downld_dwords(self,
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efuse_addr + (40U * 4U),
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mac_addr,
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ARRAY_SIZE(mac_addr));
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if (err)
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return err;
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mac_addr[0] = __swab32(mac_addr[0]);
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mac_addr[1] = __swab32(mac_addr[1]);
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}
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ether_addr_copy(mac, (u8 *)mac_addr);
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return err;
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}
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static int aq_fw2x_update_stats(struct aq_hw_s *self)
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{
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u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
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u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
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u32 stats_val;
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int err = 0;
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/* Toggle statistics bit for FW to update */
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mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
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/* Wait FW to report back */
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err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
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self, stats_val,
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orig_stats_val != (stats_val &
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BIT(CAPS_HI_STATISTICS)),
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1U, 10000U);
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if (err)
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return err;
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return hw_atl_utils_update_stats(self);
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}
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static int aq_fw2x_get_phy_temp(struct aq_hw_s *self, int *temp)
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{
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u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
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u32 temp_val = mpi_opts & HW_ATL_FW2X_CTRL_TEMPERATURE;
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u32 phy_temp_offset;
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u32 temp_res;
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int err = 0;
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u32 val;
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phy_temp_offset = self->mbox_addr + offsetof(struct hw_atl_utils_mbox,
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info.phy_temperature);
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/* Toggle statistics bit for FW to 0x36C.18 (CTRL_TEMPERATURE) */
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mpi_opts = mpi_opts ^ HW_ATL_FW2X_CTRL_TEMPERATURE;
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
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/* Wait FW to report back */
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err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,
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temp_val !=
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(val & HW_ATL_FW2X_CTRL_TEMPERATURE),
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1U, 10000U);
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err = hw_atl_utils_fw_downld_dwords(self, phy_temp_offset,
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&temp_res, 1);
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if (err)
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return err;
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/* Convert PHY temperature from 1/256 degree Celsius
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* to 1/1000 degree Celsius.
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*/
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*temp = (int16_t)(temp_res & 0xFFFF) * 1000 / 256;
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return 0;
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}
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static int aq_fw2x_set_wol(struct aq_hw_s *self, u8 *mac)
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{
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struct hw_atl_utils_fw_rpc *rpc = NULL;
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struct offload_info *info = NULL;
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u32 wol_bits = 0;
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u32 rpc_size;
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int err = 0;
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u32 val;
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if (self->aq_nic_cfg->wol & WAKE_PHY) {
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR,
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HW_ATL_FW2X_CTRL_LINK_DROP);
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readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,
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(val &
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HW_ATL_FW2X_CTRL_LINK_DROP) != 0,
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1000, 100000);
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wol_bits |= HW_ATL_FW2X_CTRL_WAKE_ON_LINK;
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}
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if (self->aq_nic_cfg->wol & WAKE_MAGIC) {
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wol_bits |= HW_ATL_FW2X_CTRL_SLEEP_PROXY |
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HW_ATL_FW2X_CTRL_WOL;
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err = hw_atl_utils_fw_rpc_wait(self, &rpc);
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if (err < 0)
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goto err_exit;
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rpc_size = sizeof(*info) +
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offsetof(struct hw_atl_utils_fw_rpc, fw2x_offloads);
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memset(rpc, 0, rpc_size);
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info = &rpc->fw2x_offloads;
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memcpy(info->mac_addr, mac, ETH_ALEN);
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info->len = sizeof(*info);
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err = hw_atl_utils_fw_rpc_call(self, rpc_size);
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if (err < 0)
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goto err_exit;
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}
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, wol_bits);
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err_exit:
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return err;
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}
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static int aq_fw2x_set_power(struct aq_hw_s *self, unsigned int power_state,
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u8 *mac)
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{
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int err = 0;
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if (self->aq_nic_cfg->wol)
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err = aq_fw2x_set_wol(self, mac);
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return err;
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}
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static int aq_fw2x_send_fw_request(struct aq_hw_s *self,
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const struct hw_fw_request_iface *fw_req,
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size_t size)
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{
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u32 ctrl2, orig_ctrl2;
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u32 dword_cnt;
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int err = 0;
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u32 val;
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/* Write data to drvIface Mailbox */
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dword_cnt = size / sizeof(u32);
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if (size % sizeof(u32))
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dword_cnt++;
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err = hw_atl_write_fwcfg_dwords(self, (void *)fw_req, dword_cnt);
|
if (err < 0)
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goto err_exit;
|
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/* Toggle statistics bit for FW to update */
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ctrl2 = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
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orig_ctrl2 = ctrl2 & BIT(CAPS_HI_FW_REQUEST);
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ctrl2 = ctrl2 ^ BIT(CAPS_HI_FW_REQUEST);
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, ctrl2);
|
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/* Wait FW to report back */
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err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,
|
orig_ctrl2 != (val &
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BIT(CAPS_HI_FW_REQUEST)),
|
1U, 10000U);
|
|
err_exit:
|
return err;
|
}
|
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static void aq_fw3x_enable_ptp(struct aq_hw_s *self, int enable)
|
{
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u32 ptp_opts = aq_hw_read_reg(self, HW_ATL_FW3X_EXT_STATE_ADDR);
|
u32 all_ptp_features = BIT(CAPS_EX_PHY_PTP_EN) |
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BIT(CAPS_EX_PTP_GPIO_EN);
|
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if (enable)
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ptp_opts |= all_ptp_features;
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else
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ptp_opts &= ~all_ptp_features;
|
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aq_hw_write_reg(self, HW_ATL_FW3X_EXT_CONTROL_ADDR, ptp_opts);
|
}
|
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static void aq_fw3x_adjust_ptp(struct aq_hw_s *self, uint64_t adj)
|
{
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aq_hw_write_reg(self, HW_ATL_FW3X_PTP_ADJ_LSW_ADDR,
|
(adj >> 0) & 0xffffffff);
|
aq_hw_write_reg(self, HW_ATL_FW3X_PTP_ADJ_MSW_ADDR,
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(adj >> 32) & 0xffffffff);
|
}
|
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static int aq_fw2x_led_control(struct aq_hw_s *self, u32 mode)
|
{
|
if (self->fw_ver_actual < HW_ATL_FW_VER_LED)
|
return -EOPNOTSUPP;
|
|
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_LED_ADDR, mode);
|
|
return 0;
|
}
|
|
static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed)
|
{
|
u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
|
|
aq_fw2x_upd_eee_rate_bits(self, &mpi_opts, speed);
|
|
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
|
|
return 0;
|
}
|
|
static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate,
|
u32 *supported_rates)
|
{
|
u32 mpi_state;
|
u32 caps_hi;
|
int err = 0;
|
u32 offset;
|
|
offset = self->mbox_addr + offsetof(struct hw_atl_utils_mbox,
|
info.caps_hi);
|
|
err = hw_atl_utils_fw_downld_dwords(self, offset, &caps_hi, 1);
|
|
if (err)
|
return err;
|
|
*supported_rates = fw2x_to_eee_mask(caps_hi);
|
|
mpi_state = aq_fw2x_state2_get(self);
|
*rate = fw2x_to_eee_mask(mpi_state);
|
|
return err;
|
}
|
|
static int aq_fw2x_renegotiate(struct aq_hw_s *self)
|
{
|
u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
|
|
mpi_opts |= BIT(CTRL_FORCE_RECONNECT);
|
|
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
|
|
return 0;
|
}
|
|
static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
|
{
|
u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
|
|
aq_fw2x_upd_flow_control_bits(self, &mpi_state,
|
self->aq_nic_cfg->fc.req);
|
|
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
|
|
return 0;
|
}
|
|
static u32 aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fcmode)
|
{
|
u32 mpi_state = aq_fw2x_state2_get(self);
|
*fcmode = 0;
|
|
if (mpi_state & HW_ATL_FW2X_CAP_PAUSE)
|
*fcmode |= AQ_NIC_FC_RX;
|
|
if (mpi_state & HW_ATL_FW2X_CAP_ASYM_PAUSE)
|
*fcmode |= AQ_NIC_FC_TX;
|
|
return 0;
|
}
|
|
static int aq_fw2x_set_phyloopback(struct aq_hw_s *self, u32 mode, bool enable)
|
{
|
u32 mpi_opts;
|
|
switch (mode) {
|
case AQ_HW_LOOPBACK_PHYINT_SYS:
|
mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
|
if (enable)
|
mpi_opts |= HW_ATL_FW2X_CTRL_INT_LOOPBACK;
|
else
|
mpi_opts &= ~HW_ATL_FW2X_CTRL_INT_LOOPBACK;
|
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
|
break;
|
case AQ_HW_LOOPBACK_PHYEXT_SYS:
|
mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
|
if (enable)
|
mpi_opts |= HW_ATL_FW2X_CTRL_EXT_LOOPBACK;
|
else
|
mpi_opts &= ~HW_ATL_FW2X_CTRL_EXT_LOOPBACK;
|
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
|
break;
|
default:
|
return -EINVAL;
|
}
|
|
return 0;
|
}
|
|
static u32 aq_fw2x_mbox_get(struct aq_hw_s *self)
|
{
|
return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR);
|
}
|
|
static u32 aq_fw2x_rpc_get(struct aq_hw_s *self)
|
{
|
return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR);
|
}
|
|
static int aq_fw2x_settings_get(struct aq_hw_s *self, u32 *addr)
|
{
|
int err = 0;
|
u32 offset;
|
|
offset = self->mbox_addr + offsetof(struct hw_atl_utils_mbox,
|
info.setting_address);
|
|
err = hw_atl_utils_fw_downld_dwords(self, offset, addr, 1);
|
|
return err;
|
}
|
|
static u32 aq_fw2x_state_get(struct aq_hw_s *self)
|
{
|
return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
|
}
|
|
static u32 aq_fw2x_state2_get(struct aq_hw_s *self)
|
{
|
return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
|
}
|
|
static int aq_fw2x_set_downshift(struct aq_hw_s *self, u32 counter)
|
{
|
int err = 0;
|
u32 mpi_opts;
|
u32 offset;
|
|
offset = offsetof(struct hw_atl_utils_settings, downshift_retry_count);
|
err = hw_atl_write_fwsettings_dwords(self, offset, &counter, 1);
|
if (err)
|
return err;
|
|
mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
|
if (counter)
|
mpi_opts |= HW_ATL_FW2X_CTRL_DOWNSHIFT;
|
else
|
mpi_opts &= ~HW_ATL_FW2X_CTRL_DOWNSHIFT;
|
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
|
|
return err;
|
}
|
|
static int aq_fw2x_set_media_detect(struct aq_hw_s *self, bool on)
|
{
|
u32 enable;
|
u32 offset;
|
|
if (self->fw_ver_actual < HW_ATL_FW_VER_MEDIA_CONTROL)
|
return -EOPNOTSUPP;
|
|
offset = offsetof(struct hw_atl_utils_settings, media_detect);
|
enable = on;
|
|
return hw_atl_write_fwsettings_dwords(self, offset, &enable, 1);
|
}
|
|
static u32 aq_fw2x_get_link_capabilities(struct aq_hw_s *self)
|
{
|
int err = 0;
|
u32 offset;
|
u32 val;
|
|
offset = self->mbox_addr +
|
offsetof(struct hw_atl_utils_mbox, info.caps_lo);
|
|
err = hw_atl_utils_fw_downld_dwords(self, offset, &val, 1);
|
|
if (err)
|
return 0;
|
|
return val;
|
}
|
|
static int aq_fw2x_send_macsec_req(struct aq_hw_s *hw,
|
struct macsec_msg_fw_request *req,
|
struct macsec_msg_fw_response *response)
|
{
|
u32 low_status, low_req = 0;
|
u32 dword_cnt;
|
u32 caps_lo;
|
u32 offset;
|
int err;
|
|
if (!req || !response)
|
return -EINVAL;
|
|
caps_lo = aq_fw2x_get_link_capabilities(hw);
|
if (!(caps_lo & BIT(CAPS_LO_MACSEC)))
|
return -EOPNOTSUPP;
|
|
/* Write macsec request to cfg memory */
|
dword_cnt = (sizeof(*req) + sizeof(u32) - 1) / sizeof(u32);
|
err = hw_atl_write_fwcfg_dwords(hw, (void *)req, dword_cnt);
|
if (err < 0)
|
return err;
|
|
/* Toggle 0x368.CAPS_LO_MACSEC bit */
|
low_req = aq_hw_read_reg(hw, HW_ATL_FW2X_MPI_CONTROL_ADDR);
|
low_req ^= HW_ATL_FW2X_CAP_MACSEC;
|
aq_hw_write_reg(hw, HW_ATL_FW2X_MPI_CONTROL_ADDR, low_req);
|
|
/* Wait FW to report back */
|
err = readx_poll_timeout_atomic(aq_fw2x_state_get, hw, low_status,
|
low_req != (low_status & BIT(CAPS_LO_MACSEC)), 1U, 10000U);
|
if (err)
|
return -EIO;
|
|
/* Read status of write operation */
|
offset = hw->rpc_addr + sizeof(u32);
|
err = hw_atl_utils_fw_downld_dwords(hw, offset, (u32 *)(void *)response,
|
sizeof(*response) / sizeof(u32));
|
|
return err;
|
}
|
|
const struct aq_fw_ops aq_fw_2x_ops = {
|
.init = aq_fw2x_init,
|
.deinit = aq_fw2x_deinit,
|
.reset = NULL,
|
.renegotiate = aq_fw2x_renegotiate,
|
.get_mac_permanent = aq_fw2x_get_mac_permanent,
|
.set_link_speed = aq_fw2x_set_link_speed,
|
.set_state = aq_fw2x_set_state,
|
.update_link_status = aq_fw2x_update_link_status,
|
.update_stats = aq_fw2x_update_stats,
|
.get_mac_temp = NULL,
|
.get_phy_temp = aq_fw2x_get_phy_temp,
|
.set_power = aq_fw2x_set_power,
|
.set_eee_rate = aq_fw2x_set_eee_rate,
|
.get_eee_rate = aq_fw2x_get_eee_rate,
|
.set_flow_control = aq_fw2x_set_flow_control,
|
.get_flow_control = aq_fw2x_get_flow_control,
|
.send_fw_request = aq_fw2x_send_fw_request,
|
.enable_ptp = aq_fw3x_enable_ptp,
|
.led_control = aq_fw2x_led_control,
|
.set_phyloopback = aq_fw2x_set_phyloopback,
|
.set_downshift = aq_fw2x_set_downshift,
|
.set_media_detect = aq_fw2x_set_media_detect,
|
.adjust_ptp = aq_fw3x_adjust_ptp,
|
.get_link_capabilities = aq_fw2x_get_link_capabilities,
|
.send_macsec_req = aq_fw2x_send_macsec_req,
|
};
|
