// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2016-2023 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#include <linux/thermal.h>
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#include "mali_kbase_ipa_counter_common_jm.h"
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#include "mali_kbase.h"
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#include <backend/gpu/mali_kbase_model_linux.h>
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/* Performance counter blocks base offsets */
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#define JM_BASE (0 * KBASE_IPA_NR_BYTES_PER_BLOCK)
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#define MEMSYS_BASE (2 * KBASE_IPA_NR_BYTES_PER_BLOCK)
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/* JM counter block offsets */
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#define JM_GPU_ACTIVE (KBASE_IPA_NR_BYTES_PER_CNT * 6)
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/* MEMSYS counter block offsets */
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#define MEMSYS_L2_ANY_LOOKUP (KBASE_IPA_NR_BYTES_PER_CNT * 25)
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/* SC counter block offsets */
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#define SC_EXEC_INSTR_FMA (KBASE_IPA_NR_BYTES_PER_CNT * 27)
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#define SC_EXEC_INSTR_COUNT (KBASE_IPA_NR_BYTES_PER_CNT * 28)
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#define SC_EXEC_INSTR_MSG (KBASE_IPA_NR_BYTES_PER_CNT * 30)
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#define SC_TEX_FILT_NUM_OPERATIONS (KBASE_IPA_NR_BYTES_PER_CNT * 39)
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#define SC_TEX_COORD_ISSUE (KBASE_IPA_NR_BYTES_PER_CNT * 40)
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#define SC_TEX_TFCH_NUM_OPERATIONS (KBASE_IPA_NR_BYTES_PER_CNT * 42)
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#define SC_VARY_INSTR (KBASE_IPA_NR_BYTES_PER_CNT * 49)
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#define SC_BEATS_WR_TIB (KBASE_IPA_NR_BYTES_PER_CNT * 62)
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/**
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* kbase_g7x_power_model_get_jm_counter() - get performance counter offset
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* inside the Job Manager block
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* @model_data: pointer to GPU model data.
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* @counter_block_offset: offset in bytes of the performance counter inside
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* the Job Manager block.
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*
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* Return: Block offset in bytes of the required performance counter.
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*/
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static u32 kbase_g7x_power_model_get_jm_counter(struct kbase_ipa_model_vinstr_data *model_data,
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u32 counter_block_offset)
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{
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return JM_BASE + counter_block_offset;
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}
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/**
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* kbase_g7x_power_model_get_memsys_counter() - get performance counter offset
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* inside the Memory System block
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* @model_data: pointer to GPU model data.
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* @counter_block_offset: offset in bytes of the performance counter inside
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* the (first) Memory System block.
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*
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* Return: Block offset in bytes of the required performance counter.
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*/
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static u32 kbase_g7x_power_model_get_memsys_counter(struct kbase_ipa_model_vinstr_data *model_data,
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u32 counter_block_offset)
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{
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/* The base address of Memory System performance counters is always the same, although their number
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* may vary based on the number of cores. For the moment it's ok to return a constant.
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*/
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return MEMSYS_BASE + counter_block_offset;
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}
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/**
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* kbase_g7x_power_model_get_sc_counter() - get performance counter offset
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* inside the Shader Cores block
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* @model_data: pointer to GPU model data.
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* @counter_block_offset: offset in bytes of the performance counter inside
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* the (first) Shader Cores block.
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*
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* Return: Block offset in bytes of the required performance counter.
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*/
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static u32 kbase_g7x_power_model_get_sc_counter(struct kbase_ipa_model_vinstr_data *model_data,
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u32 counter_block_offset)
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{
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#if IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI)
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const u32 sc_base = MEMSYS_BASE +
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(KBASE_DUMMY_MODEL_MAX_MEMSYS_BLOCKS *
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KBASE_IPA_NR_BYTES_PER_BLOCK);
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#else
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const u32 sc_base = MEMSYS_BASE +
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(model_data->kbdev->gpu_props.props.l2_props.num_l2_slices *
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KBASE_IPA_NR_BYTES_PER_BLOCK);
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#endif
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return sc_base + counter_block_offset;
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}
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/**
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* kbase_g7x_sum_all_memsys_blocks() - calculate energy for a single Memory
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* System performance counter.
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* @model_data: pointer to GPU model data.
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* @coeff: default value of coefficient for IPA group.
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* @counter_block_offset: offset in bytes of the counter inside the block it
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* belongs to.
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*
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* Return: Energy estimation for a single Memory System performance counter.
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*/
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static s64 kbase_g7x_sum_all_memsys_blocks(
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struct kbase_ipa_model_vinstr_data *model_data,
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s32 coeff,
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u32 counter_block_offset)
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{
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u32 counter;
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counter = kbase_g7x_power_model_get_memsys_counter(model_data,
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counter_block_offset);
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return kbase_ipa_sum_all_memsys_blocks(model_data, coeff, counter);
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}
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/**
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* kbase_g7x_sum_all_shader_cores() - calculate energy for a Shader Cores
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* performance counter for all cores.
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* @model_data: pointer to GPU model data.
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* @coeff: default value of coefficient for IPA group.
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* @counter_block_offset: offset in bytes of the counter inside the block it
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* belongs to.
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*
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* Return: Energy estimation for a Shader Cores performance counter for all
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* cores.
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*/
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static s64 kbase_g7x_sum_all_shader_cores(
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struct kbase_ipa_model_vinstr_data *model_data,
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s32 coeff,
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u32 counter_block_offset)
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{
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u32 counter;
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counter = kbase_g7x_power_model_get_sc_counter(model_data,
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counter_block_offset);
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return kbase_ipa_sum_all_shader_cores(model_data, coeff, counter);
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}
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/**
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* kbase_g7x_jm_single_counter() - calculate energy for a single Job Manager performance counter.
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* @model_data: pointer to GPU model data.
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* @coeff: default value of coefficient for IPA group.
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* @counter_block_offset: offset in bytes of the counter inside the block it belongs to.
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*
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* Return: Energy estimation for a single Job Manager performance counter.
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*/
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static s64 kbase_g7x_jm_single_counter(
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struct kbase_ipa_model_vinstr_data *model_data,
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s32 coeff,
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u32 counter_block_offset)
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{
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u32 counter;
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counter = kbase_g7x_power_model_get_jm_counter(model_data,
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counter_block_offset);
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return kbase_ipa_single_counter(model_data, coeff, counter);
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}
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/**
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* kbase_g7x_get_active_cycles() - return the GPU_ACTIVE counter
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* @model_data: pointer to GPU model data.
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*
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* Return: the number of cycles the GPU was active during the counter sampling
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* period.
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*/
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static u32 kbase_g7x_get_active_cycles(
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struct kbase_ipa_model_vinstr_data *model_data)
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{
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u32 counter = kbase_g7x_power_model_get_jm_counter(model_data, JM_GPU_ACTIVE);
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/* Counters are only 32-bit, so we can safely multiply by 1 then cast
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* the 64-bit result back to a u32.
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*/
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return kbase_ipa_single_counter(model_data, 1, counter);
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}
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/* Table of IPA group definitions.
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*
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* For each IPA group, this table defines a function to access the given performance block counter (or counters,
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* if the operation needs to be iterated on multiple blocks) and calculate energy estimation.
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*/
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static const struct kbase_ipa_group ipa_groups_def_g71[] = {
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{
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.name = "l2_access",
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.default_value = 526300,
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.op = kbase_g7x_sum_all_memsys_blocks,
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.counter_block_offset = MEMSYS_L2_ANY_LOOKUP,
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},
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{
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.name = "exec_instr_count",
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.default_value = 301100,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_EXEC_INSTR_COUNT,
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},
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{
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.name = "tex_issue",
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.default_value = 197400,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_TEX_COORD_ISSUE,
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},
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{
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.name = "tile_wb",
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.default_value = -156400,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_BEATS_WR_TIB,
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},
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{
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.name = "gpu_active",
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.default_value = 115800,
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.op = kbase_g7x_jm_single_counter,
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.counter_block_offset = JM_GPU_ACTIVE,
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},
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};
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static const struct kbase_ipa_group ipa_groups_def_g72[] = {
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{
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.name = "l2_access",
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.default_value = 393000,
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.op = kbase_g7x_sum_all_memsys_blocks,
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.counter_block_offset = MEMSYS_L2_ANY_LOOKUP,
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},
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{
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.name = "exec_instr_count",
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.default_value = 227000,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_EXEC_INSTR_COUNT,
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},
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{
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.name = "tex_issue",
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.default_value = 181900,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_TEX_COORD_ISSUE,
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},
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{
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.name = "tile_wb",
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.default_value = -120200,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_BEATS_WR_TIB,
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},
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{
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.name = "gpu_active",
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.default_value = 133100,
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.op = kbase_g7x_jm_single_counter,
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.counter_block_offset = JM_GPU_ACTIVE,
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},
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};
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static const struct kbase_ipa_group ipa_groups_def_g76[] = {
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{
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.name = "gpu_active",
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.default_value = 122000,
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.op = kbase_g7x_jm_single_counter,
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.counter_block_offset = JM_GPU_ACTIVE,
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},
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{
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.name = "exec_instr_count",
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.default_value = 488900,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_EXEC_INSTR_COUNT,
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},
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{
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.name = "vary_instr",
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.default_value = 212100,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_VARY_INSTR,
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},
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{
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.name = "tex_tfch_num_operations",
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.default_value = 288000,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_TEX_TFCH_NUM_OPERATIONS,
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},
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{
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.name = "l2_access",
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.default_value = 378100,
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.op = kbase_g7x_sum_all_memsys_blocks,
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.counter_block_offset = MEMSYS_L2_ANY_LOOKUP,
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},
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};
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static const struct kbase_ipa_group ipa_groups_def_g52_r1[] = {
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{
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.name = "gpu_active",
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.default_value = 224200,
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.op = kbase_g7x_jm_single_counter,
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.counter_block_offset = JM_GPU_ACTIVE,
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},
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{
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.name = "exec_instr_count",
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.default_value = 384700,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_EXEC_INSTR_COUNT,
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},
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{
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.name = "vary_instr",
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.default_value = 271900,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_VARY_INSTR,
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},
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{
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.name = "tex_tfch_num_operations",
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.default_value = 477700,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_TEX_TFCH_NUM_OPERATIONS,
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},
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{
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.name = "l2_access",
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.default_value = 551400,
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.op = kbase_g7x_sum_all_memsys_blocks,
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.counter_block_offset = MEMSYS_L2_ANY_LOOKUP,
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},
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};
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static const struct kbase_ipa_group ipa_groups_def_g51[] = {
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{
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.name = "gpu_active",
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.default_value = 201400,
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.op = kbase_g7x_jm_single_counter,
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.counter_block_offset = JM_GPU_ACTIVE,
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},
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{
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.name = "exec_instr_count",
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.default_value = 392700,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_EXEC_INSTR_COUNT,
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},
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{
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.name = "vary_instr",
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.default_value = 274000,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_VARY_INSTR,
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},
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{
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.name = "tex_tfch_num_operations",
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.default_value = 528000,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_TEX_TFCH_NUM_OPERATIONS,
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},
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{
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.name = "l2_access",
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.default_value = 506400,
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.op = kbase_g7x_sum_all_memsys_blocks,
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.counter_block_offset = MEMSYS_L2_ANY_LOOKUP,
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},
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};
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static const struct kbase_ipa_group ipa_groups_def_g77[] = {
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{
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.name = "l2_access",
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.default_value = 710800,
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.op = kbase_g7x_sum_all_memsys_blocks,
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.counter_block_offset = MEMSYS_L2_ANY_LOOKUP,
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},
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{
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.name = "exec_instr_msg",
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.default_value = 2375300,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_EXEC_INSTR_MSG,
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},
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{
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.name = "exec_instr_fma",
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.default_value = 656100,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_EXEC_INSTR_FMA,
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},
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{
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.name = "tex_filt_num_operations",
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.default_value = 318800,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_TEX_FILT_NUM_OPERATIONS,
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},
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{
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.name = "gpu_active",
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.default_value = 172800,
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.op = kbase_g7x_jm_single_counter,
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.counter_block_offset = JM_GPU_ACTIVE,
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},
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};
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static const struct kbase_ipa_group ipa_groups_def_tbex[] = {
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{
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.name = "l2_access",
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.default_value = 599800,
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.op = kbase_g7x_sum_all_memsys_blocks,
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.counter_block_offset = MEMSYS_L2_ANY_LOOKUP,
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},
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{
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.name = "exec_instr_msg",
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.default_value = 1830200,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_EXEC_INSTR_MSG,
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},
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{
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.name = "exec_instr_fma",
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.default_value = 407300,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_EXEC_INSTR_FMA,
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},
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{
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.name = "tex_filt_num_operations",
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.default_value = 224500,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_TEX_FILT_NUM_OPERATIONS,
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},
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{
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.name = "gpu_active",
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.default_value = 153800,
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.op = kbase_g7x_jm_single_counter,
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.counter_block_offset = JM_GPU_ACTIVE,
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},
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};
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static const struct kbase_ipa_group ipa_groups_def_tbax[] = {
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{
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.name = "l2_access",
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.default_value = 599800,
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.op = kbase_g7x_sum_all_memsys_blocks,
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.counter_block_offset = MEMSYS_L2_ANY_LOOKUP,
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},
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{
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.name = "exec_instr_msg",
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.default_value = 1830200,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_EXEC_INSTR_MSG,
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},
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{
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.name = "exec_instr_fma",
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.default_value = 407300,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_EXEC_INSTR_FMA,
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},
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{
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.name = "tex_filt_num_operations",
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.default_value = 224500,
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.op = kbase_g7x_sum_all_shader_cores,
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.counter_block_offset = SC_TEX_FILT_NUM_OPERATIONS,
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},
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{
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.name = "gpu_active",
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.default_value = 153800,
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.op = kbase_g7x_jm_single_counter,
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.counter_block_offset = JM_GPU_ACTIVE,
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},
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};
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#define IPA_POWER_MODEL_OPS(gpu, init_token) \
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static const struct kbase_ipa_model_ops kbase_##gpu##_ipa_model_ops = { \
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.name = "mali-" #gpu "-power-model", \
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.init = kbase_##init_token##_power_model_init, \
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.term = kbase_ipa_vinstr_common_model_term, \
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.get_dynamic_coeff = kbase_ipa_vinstr_dynamic_coeff, \
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.reset_counter_data = kbase_ipa_vinstr_reset_data, \
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}
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#define STANDARD_POWER_MODEL(gpu, reference_voltage) \
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static int kbase_ ## gpu ## _power_model_init(\
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struct kbase_ipa_model *model) \
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{ \
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BUILD_BUG_ON(ARRAY_SIZE(ipa_groups_def_ ## gpu) > \
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KBASE_IPA_MAX_GROUP_DEF_NUM); \
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return kbase_ipa_vinstr_common_model_init(model, \
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ipa_groups_def_ ## gpu, \
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ARRAY_SIZE(ipa_groups_def_ ## gpu), \
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kbase_g7x_get_active_cycles, \
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(reference_voltage)); \
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} \
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IPA_POWER_MODEL_OPS(gpu, gpu)
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#define ALIAS_POWER_MODEL(gpu, as_gpu) \
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IPA_POWER_MODEL_OPS(gpu, as_gpu)
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STANDARD_POWER_MODEL(g71, 800);
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STANDARD_POWER_MODEL(g72, 800);
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STANDARD_POWER_MODEL(g76, 800);
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STANDARD_POWER_MODEL(g52_r1, 1000);
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STANDARD_POWER_MODEL(g51, 1000);
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STANDARD_POWER_MODEL(g77, 1000);
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STANDARD_POWER_MODEL(tbex, 1000);
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STANDARD_POWER_MODEL(tbax, 1000);
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/* g52 is an alias of g76 (TNOX) for IPA */
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ALIAS_POWER_MODEL(g52, g76);
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/* tnax is an alias of g77 (TTRX) for IPA */
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ALIAS_POWER_MODEL(tnax, g77);
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static const struct kbase_ipa_model_ops *ipa_counter_model_ops[] = {
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&kbase_g71_ipa_model_ops,
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&kbase_g72_ipa_model_ops,
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&kbase_g76_ipa_model_ops,
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&kbase_g52_ipa_model_ops,
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&kbase_g52_r1_ipa_model_ops,
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&kbase_g51_ipa_model_ops,
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&kbase_g77_ipa_model_ops,
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&kbase_tnax_ipa_model_ops,
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&kbase_tbex_ipa_model_ops,
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&kbase_tbax_ipa_model_ops
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};
|
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const struct kbase_ipa_model_ops *kbase_ipa_counter_model_ops_find(
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struct kbase_device *kbdev, const char *name)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ipa_counter_model_ops); ++i) {
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const struct kbase_ipa_model_ops *ops =
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ipa_counter_model_ops[i];
|
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if (!strcmp(ops->name, name))
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return ops;
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}
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dev_err(kbdev->dev, "power model \'%s\' not found\n", name);
|
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return NULL;
|
}
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const char *kbase_ipa_counter_model_name_from_id(u32 gpu_id)
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{
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const u32 prod_id =
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(gpu_id & GPU_ID_VERSION_PRODUCT_ID) >> KBASE_GPU_ID_VERSION_PRODUCT_ID_SHIFT;
|
|
switch (GPU_ID2_MODEL_MATCH_VALUE(prod_id)) {
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case GPU_ID2_PRODUCT_TMIX:
|
return "mali-g71-power-model";
|
case GPU_ID2_PRODUCT_THEX:
|
return "mali-g72-power-model";
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case GPU_ID2_PRODUCT_TNOX:
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return "mali-g76-power-model";
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case GPU_ID2_PRODUCT_TSIX:
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return "mali-g51-power-model";
|
case GPU_ID2_PRODUCT_TGOX:
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if ((gpu_id & GPU_ID2_VERSION_MAJOR) ==
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(0 << GPU_ID2_VERSION_MAJOR_SHIFT))
|
/* g52 aliased to g76 power-model's ops */
|
return "mali-g52-power-model";
|
else
|
return "mali-g52_r1-power-model";
|
case GPU_ID2_PRODUCT_TNAX:
|
return "mali-tnax-power-model";
|
case GPU_ID2_PRODUCT_TTRX:
|
return "mali-g77-power-model";
|
case GPU_ID2_PRODUCT_TBEX:
|
return "mali-tbex-power-model";
|
case GPU_ID2_PRODUCT_TBAX:
|
return "mali-tbax-power-model";
|
default:
|
return NULL;
|
}
|
}
|
