// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#include "mali_kbase_ipa_counter_common_csf.h"
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#include "mali_kbase.h"
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/* MEMSYS counter block offsets */
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#define L2_RD_MSG_IN_CU (13)
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#define L2_RD_MSG_IN (16)
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#define L2_WR_MSG_IN (18)
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#define L2_SNP_MSG_IN (20)
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#define L2_RD_MSG_OUT (22)
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#define L2_READ_LOOKUP (26)
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#define L2_EXT_READ_NOSNP (30)
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#define L2_EXT_WRITE_NOSNP_FULL (43)
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/* SC counter block offsets */
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#define FRAG_STARVING (8)
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#define FRAG_PARTIAL_QUADS_RAST (10)
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#define FRAG_QUADS_EZS_UPDATE (13)
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#define FULL_QUAD_WARPS (21)
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#define EXEC_INSTR_FMA (27)
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#define EXEC_INSTR_CVT (28)
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#define EXEC_INSTR_SFU (29)
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#define EXEC_INSTR_MSG (30)
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#define TEX_FILT_NUM_OPS (39)
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#define LS_MEM_READ_SHORT (45)
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#define LS_MEM_WRITE_SHORT (47)
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#define VARY_SLOT_16 (51)
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#define BEATS_RD_LSC_EXT (57)
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#define BEATS_RD_TEX (58)
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#define BEATS_RD_TEX_EXT (59)
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#define FRAG_QUADS_COARSE (68)
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/* Tiler counter block offsets */
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#define IDVS_POS_SHAD_STALL (23)
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#define PREFETCH_STALL (25)
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#define VFETCH_POS_READ_WAIT (29)
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#define VFETCH_VERTEX_WAIT (30)
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#define PRIMASSY_STALL (32)
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#define IDVS_VAR_SHAD_STALL (38)
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#define ITER_STALL (40)
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#define PMGR_PTR_RD_STALL (48)
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#define COUNTER_DEF(cnt_name, coeff, cnt_idx, block_type) \
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{ \
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.name = cnt_name, \
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.coeff_default_value = coeff, \
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.counter_block_offset = cnt_idx, \
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.counter_block_type = block_type, \
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}
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#define MEMSYS_COUNTER_DEF(cnt_name, coeff, cnt_idx) \
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COUNTER_DEF(cnt_name, coeff, cnt_idx, KBASE_IPA_CORE_TYPE_MEMSYS)
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#define SC_COUNTER_DEF(cnt_name, coeff, cnt_idx) \
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COUNTER_DEF(cnt_name, coeff, cnt_idx, KBASE_IPA_CORE_TYPE_SHADER)
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#define TILER_COUNTER_DEF(cnt_name, coeff, cnt_idx) \
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COUNTER_DEF(cnt_name, coeff, cnt_idx, KBASE_IPA_CORE_TYPE_TILER)
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/* Tables of description of HW counters used by IPA counter model.
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*
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* These tables provide a description of each performance counter
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* used by the top level counter model for energy estimation.
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*/
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static const struct kbase_ipa_counter ipa_top_level_cntrs_def_todx[] = {
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MEMSYS_COUNTER_DEF("l2_rd_msg_in", 295631, L2_RD_MSG_IN),
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MEMSYS_COUNTER_DEF("l2_ext_write_nosnp_ull", 325168, L2_EXT_WRITE_NOSNP_FULL),
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TILER_COUNTER_DEF("prefetch_stall", 145435, PREFETCH_STALL),
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TILER_COUNTER_DEF("idvs_var_shad_stall", -171917, IDVS_VAR_SHAD_STALL),
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TILER_COUNTER_DEF("idvs_pos_shad_stall", 109980, IDVS_POS_SHAD_STALL),
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TILER_COUNTER_DEF("vfetch_pos_read_wait", -119118, VFETCH_POS_READ_WAIT),
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};
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static const struct kbase_ipa_counter ipa_top_level_cntrs_def_tgrx[] = {
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MEMSYS_COUNTER_DEF("l2_rd_msg_in", 295631, L2_RD_MSG_IN),
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MEMSYS_COUNTER_DEF("l2_ext_write_nosnp_ull", 325168, L2_EXT_WRITE_NOSNP_FULL),
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TILER_COUNTER_DEF("prefetch_stall", 145435, PREFETCH_STALL),
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TILER_COUNTER_DEF("idvs_var_shad_stall", -171917, IDVS_VAR_SHAD_STALL),
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TILER_COUNTER_DEF("idvs_pos_shad_stall", 109980, IDVS_POS_SHAD_STALL),
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TILER_COUNTER_DEF("vfetch_pos_read_wait", -119118, VFETCH_POS_READ_WAIT),
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};
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static const struct kbase_ipa_counter ipa_top_level_cntrs_def_tvax[] = {
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MEMSYS_COUNTER_DEF("l2_rd_msg_out", 491414, L2_RD_MSG_OUT),
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MEMSYS_COUNTER_DEF("l2_wr_msg_in", 408645, L2_WR_MSG_IN),
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TILER_COUNTER_DEF("iter_stall", 893324, ITER_STALL),
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TILER_COUNTER_DEF("pmgr_ptr_rd_stall", -975117, PMGR_PTR_RD_STALL),
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TILER_COUNTER_DEF("idvs_pos_shad_stall", 22555, IDVS_POS_SHAD_STALL),
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};
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static const struct kbase_ipa_counter ipa_top_level_cntrs_def_ttux[] = {
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MEMSYS_COUNTER_DEF("l2_rd_msg_in", 800836, L2_RD_MSG_IN),
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MEMSYS_COUNTER_DEF("l2_wr_msg_in", 415579, L2_WR_MSG_IN),
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MEMSYS_COUNTER_DEF("l2_read_lookup", -198124, L2_READ_LOOKUP),
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TILER_COUNTER_DEF("idvs_pos_shad_stall", 117358, IDVS_POS_SHAD_STALL),
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TILER_COUNTER_DEF("vfetch_vertex_wait", -391964, VFETCH_VERTEX_WAIT),
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};
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static const struct kbase_ipa_counter ipa_top_level_cntrs_def_ttix[] = {
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TILER_COUNTER_DEF("primassy_stall", 471953, PRIMASSY_STALL),
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TILER_COUNTER_DEF("idvs_var_shad_stall", -460559, IDVS_VAR_SHAD_STALL),
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MEMSYS_COUNTER_DEF("l2_rd_msg_in_cu", -6189604, L2_RD_MSG_IN_CU),
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MEMSYS_COUNTER_DEF("l2_snp_msg_in", 6289609, L2_SNP_MSG_IN),
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MEMSYS_COUNTER_DEF("l2_ext_read_nosnp", 512341, L2_EXT_READ_NOSNP),
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};
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/* These tables provide a description of each performance counter
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* used by the shader cores counter model for energy estimation.
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*/
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static const struct kbase_ipa_counter ipa_shader_core_cntrs_def_todx[] = {
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SC_COUNTER_DEF("exec_instr_fma", 505449, EXEC_INSTR_FMA),
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SC_COUNTER_DEF("tex_filt_num_operations", 574869, TEX_FILT_NUM_OPS),
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SC_COUNTER_DEF("ls_mem_read_short", 60917, LS_MEM_READ_SHORT),
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SC_COUNTER_DEF("frag_quads_ezs_update", 694555, FRAG_QUADS_EZS_UPDATE),
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SC_COUNTER_DEF("ls_mem_write_short", 698290, LS_MEM_WRITE_SHORT),
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SC_COUNTER_DEF("vary_slot_16", 181069, VARY_SLOT_16),
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};
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static const struct kbase_ipa_counter ipa_shader_core_cntrs_def_tgrx[] = {
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SC_COUNTER_DEF("exec_instr_fma", 505449, EXEC_INSTR_FMA),
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SC_COUNTER_DEF("tex_filt_num_operations", 574869, TEX_FILT_NUM_OPS),
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SC_COUNTER_DEF("ls_mem_read_short", 60917, LS_MEM_READ_SHORT),
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SC_COUNTER_DEF("frag_quads_ezs_update", 694555, FRAG_QUADS_EZS_UPDATE),
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SC_COUNTER_DEF("ls_mem_write_short", 698290, LS_MEM_WRITE_SHORT),
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SC_COUNTER_DEF("vary_slot_16", 181069, VARY_SLOT_16),
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};
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static const struct kbase_ipa_counter ipa_shader_core_cntrs_def_tvax[] = {
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SC_COUNTER_DEF("tex_filt_num_operations", 142536, TEX_FILT_NUM_OPS),
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SC_COUNTER_DEF("exec_instr_fma", 243497, EXEC_INSTR_FMA),
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SC_COUNTER_DEF("exec_instr_msg", 1344410, EXEC_INSTR_MSG),
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SC_COUNTER_DEF("vary_slot_16", -119612, VARY_SLOT_16),
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SC_COUNTER_DEF("frag_partial_quads_rast", 676201, FRAG_PARTIAL_QUADS_RAST),
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SC_COUNTER_DEF("frag_starving", 62421, FRAG_STARVING),
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};
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static const struct kbase_ipa_counter ipa_shader_core_cntrs_def_ttux[] = {
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SC_COUNTER_DEF("exec_instr_fma", 457012, EXEC_INSTR_FMA),
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SC_COUNTER_DEF("tex_filt_num_operations", 441911, TEX_FILT_NUM_OPS),
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SC_COUNTER_DEF("ls_mem_read_short", 322525, LS_MEM_READ_SHORT),
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SC_COUNTER_DEF("full_quad_warps", 844124, FULL_QUAD_WARPS),
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SC_COUNTER_DEF("exec_instr_cvt", 226411, EXEC_INSTR_CVT),
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SC_COUNTER_DEF("frag_quads_ezs_update", 372032, FRAG_QUADS_EZS_UPDATE),
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};
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static const struct kbase_ipa_counter ipa_shader_core_cntrs_def_ttix[] = {
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SC_COUNTER_DEF("exec_instr_fma", 192642, EXEC_INSTR_FMA),
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SC_COUNTER_DEF("exec_instr_msg", 1326465, EXEC_INSTR_MSG),
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SC_COUNTER_DEF("beats_rd_tex", 163518, BEATS_RD_TEX),
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SC_COUNTER_DEF("beats_rd_lsc_ext", 127475, BEATS_RD_LSC_EXT),
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SC_COUNTER_DEF("frag_quads_coarse", -36247, FRAG_QUADS_COARSE),
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SC_COUNTER_DEF("ls_mem_write_short", 51547, LS_MEM_WRITE_SHORT),
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SC_COUNTER_DEF("beats_rd_tex_ext", -43370, BEATS_RD_TEX_EXT),
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SC_COUNTER_DEF("exec_instr_sfu", 31583, EXEC_INSTR_SFU),
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};
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#define IPA_POWER_MODEL_OPS(gpu, init_token) \
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const struct kbase_ipa_model_ops kbase_ ## gpu ## _ipa_model_ops = { \
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.name = "mali-" #gpu "-power-model", \
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.init = kbase_ ## init_token ## _power_model_init, \
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.term = kbase_ipa_counter_common_model_term, \
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.get_dynamic_coeff = kbase_ipa_counter_dynamic_coeff, \
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.reset_counter_data = kbase_ipa_counter_reset_data, \
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}; \
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KBASE_EXPORT_TEST_API(kbase_ ## gpu ## _ipa_model_ops)
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#define STANDARD_POWER_MODEL(gpu, reference_voltage) \
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static int kbase_ ## gpu ## _power_model_init(\
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struct kbase_ipa_model *model) \
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{ \
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BUILD_BUG_ON((1 + \
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ARRAY_SIZE(ipa_top_level_cntrs_def_ ## gpu) +\
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ARRAY_SIZE(ipa_shader_core_cntrs_def_ ## gpu)) > \
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KBASE_IPA_MAX_COUNTER_DEF_NUM); \
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return kbase_ipa_counter_common_model_init(model, \
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ipa_top_level_cntrs_def_ ## gpu, \
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ARRAY_SIZE(ipa_top_level_cntrs_def_ ## gpu), \
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ipa_shader_core_cntrs_def_ ## gpu, \
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ARRAY_SIZE(ipa_shader_core_cntrs_def_ ## gpu), \
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(reference_voltage)); \
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} \
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IPA_POWER_MODEL_OPS(gpu, gpu)
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#define ALIAS_POWER_MODEL(gpu, as_gpu) \
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IPA_POWER_MODEL_OPS(gpu, as_gpu)
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/* Reference voltage value is 750 mV. */
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STANDARD_POWER_MODEL(todx, 750);
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STANDARD_POWER_MODEL(tgrx, 750);
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STANDARD_POWER_MODEL(tvax, 750);
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STANDARD_POWER_MODEL(ttux, 750);
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/* Reference voltage value is 550 mV. */
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STANDARD_POWER_MODEL(ttix, 550);
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/* Assuming LODX is an alias of TODX for IPA */
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ALIAS_POWER_MODEL(lodx, todx);
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/* Assuming LTUX is an alias of TTUX for IPA */
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ALIAS_POWER_MODEL(ltux, ttux);
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/* Assuming LTUX is an alias of TTUX for IPA */
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ALIAS_POWER_MODEL(ltix, ttix);
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static const struct kbase_ipa_model_ops *ipa_counter_model_ops[] = {
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&kbase_todx_ipa_model_ops, &kbase_lodx_ipa_model_ops,
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&kbase_tgrx_ipa_model_ops, &kbase_tvax_ipa_model_ops,
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&kbase_ttux_ipa_model_ops, &kbase_ltux_ipa_model_ops,
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&kbase_ttix_ipa_model_ops, &kbase_ltix_ipa_model_ops,
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};
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const struct kbase_ipa_model_ops *kbase_ipa_counter_model_ops_find(
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struct kbase_device *kbdev, const char *name)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ipa_counter_model_ops); ++i) {
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const struct kbase_ipa_model_ops *ops =
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ipa_counter_model_ops[i];
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if (!strcmp(ops->name, name))
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return ops;
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}
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dev_err(kbdev->dev, "power model \'%s\' not found\n", name);
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return NULL;
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}
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const char *kbase_ipa_counter_model_name_from_id(u32 gpu_id)
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{
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const u32 prod_id =
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(gpu_id & GPU_ID_VERSION_PRODUCT_ID) >> KBASE_GPU_ID_VERSION_PRODUCT_ID_SHIFT;
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switch (GPU_ID2_MODEL_MATCH_VALUE(prod_id)) {
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case GPU_ID2_PRODUCT_TODX:
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return "mali-todx-power-model";
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case GPU_ID2_PRODUCT_LODX:
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return "mali-lodx-power-model";
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case GPU_ID2_PRODUCT_TGRX:
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return "mali-tgrx-power-model";
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case GPU_ID2_PRODUCT_TVAX:
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return "mali-tvax-power-model";
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case GPU_ID2_PRODUCT_TTUX:
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return "mali-ttux-power-model";
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case GPU_ID2_PRODUCT_LTUX:
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return "mali-ltux-power-model";
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case GPU_ID2_PRODUCT_TTIX:
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return "mali-ttix-power-model";
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case GPU_ID2_PRODUCT_LTIX:
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return "mali-ltix-power-model";
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default:
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return NULL;
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}
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}
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