// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2017-2022 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#include "mali_kbase_ipa_counter_common_jm.h"
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#include "ipa/mali_kbase_ipa_debugfs.h"
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#define DEFAULT_SCALING_FACTOR 5
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/* If the value of GPU_ACTIVE is below this, use the simple model
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* instead, to avoid extrapolating small amounts of counter data across
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* large sample periods.
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*/
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#define DEFAULT_MIN_SAMPLE_CYCLES 10000
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/**
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* kbase_ipa_read_hwcnt() - read a counter value
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* @model_data: pointer to model data
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* @offset: offset, in bytes, into vinstr buffer
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*
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* Return: A 32-bit counter value. Range: 0 < value < 2^27 (worst case would be
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* incrementing every cycle over a ~100ms sample period at a high frequency,
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* e.g. 1 GHz: 2^30 * 0.1seconds ~= 2^27.
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*/
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static inline u32 kbase_ipa_read_hwcnt(
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struct kbase_ipa_model_vinstr_data *model_data,
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u32 offset)
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{
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u8 *p = (u8 *)model_data->dump_buf.dump_buf;
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u64 val = *(u64 *)&p[offset];
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return (val > U32_MAX) ? U32_MAX : (u32)val;
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}
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static inline s64 kbase_ipa_add_saturate(s64 a, s64 b)
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{
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s64 rtn;
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if (a > 0 && (S64_MAX - a) < b)
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rtn = S64_MAX;
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else if (a < 0 && (S64_MIN - a) > b)
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rtn = S64_MIN;
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else
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rtn = a + b;
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return rtn;
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}
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s64 kbase_ipa_sum_all_shader_cores(
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struct kbase_ipa_model_vinstr_data *model_data,
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s32 coeff, u32 counter)
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{
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struct kbase_device *kbdev = model_data->kbdev;
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u64 core_mask;
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u32 base = 0;
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s64 ret = 0;
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core_mask = kbdev->gpu_props.props.coherency_info.group[0].core_mask;
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while (core_mask != 0ull) {
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if ((core_mask & 1ull) != 0ull) {
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/* 0 < counter_value < 2^27 */
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u32 counter_value = kbase_ipa_read_hwcnt(model_data,
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base + counter);
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/* 0 < ret < 2^27 * max_num_cores = 2^32 */
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ret = kbase_ipa_add_saturate(ret, counter_value);
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}
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base += KBASE_IPA_NR_BYTES_PER_BLOCK;
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core_mask >>= 1;
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}
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/* Range: -2^54 < ret * coeff < 2^54 */
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return ret * coeff;
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}
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s64 kbase_ipa_sum_all_memsys_blocks(
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struct kbase_ipa_model_vinstr_data *model_data,
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s32 coeff, u32 counter)
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{
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struct kbase_device *kbdev = model_data->kbdev;
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const u32 num_blocks = kbdev->gpu_props.props.l2_props.num_l2_slices;
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u32 base = 0;
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s64 ret = 0;
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u32 i;
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for (i = 0; i < num_blocks; i++) {
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/* 0 < counter_value < 2^27 */
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u32 counter_value = kbase_ipa_read_hwcnt(model_data,
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base + counter);
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/* 0 < ret < 2^27 * max_num_memsys_blocks = 2^29 */
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ret = kbase_ipa_add_saturate(ret, counter_value);
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base += KBASE_IPA_NR_BYTES_PER_BLOCK;
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}
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/* Range: -2^51 < ret * coeff < 2^51 */
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return ret * coeff;
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}
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s64 kbase_ipa_single_counter(
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struct kbase_ipa_model_vinstr_data *model_data,
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s32 coeff, u32 counter)
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{
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/* Range: 0 < counter_value < 2^27 */
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const u32 counter_value = kbase_ipa_read_hwcnt(model_data, counter);
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/* Range: -2^49 < ret < 2^49 */
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return counter_value * (s64) coeff;
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}
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int kbase_ipa_attach_vinstr(struct kbase_ipa_model_vinstr_data *model_data)
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{
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int errcode;
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struct kbase_device *kbdev = model_data->kbdev;
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struct kbase_hwcnt_virtualizer *hvirt = kbdev->hwcnt_gpu_virt;
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struct kbase_hwcnt_enable_map enable_map;
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const struct kbase_hwcnt_metadata *metadata =
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kbase_hwcnt_virtualizer_metadata(hvirt);
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if (!metadata)
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return -1;
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errcode = kbase_hwcnt_enable_map_alloc(metadata, &enable_map);
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if (errcode) {
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dev_err(kbdev->dev, "Failed to allocate IPA enable map");
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return errcode;
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}
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kbase_hwcnt_enable_map_enable_all(&enable_map);
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/* Disable cycle counter only. */
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enable_map.clk_enable_map = 0;
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errcode = kbase_hwcnt_virtualizer_client_create(
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hvirt, &enable_map, &model_data->hvirt_cli);
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kbase_hwcnt_enable_map_free(&enable_map);
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if (errcode) {
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dev_err(kbdev->dev, "Failed to register IPA with virtualizer");
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model_data->hvirt_cli = NULL;
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return errcode;
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}
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errcode = kbase_hwcnt_dump_buffer_alloc(
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metadata, &model_data->dump_buf);
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if (errcode) {
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dev_err(kbdev->dev, "Failed to allocate IPA dump buffer");
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kbase_hwcnt_virtualizer_client_destroy(model_data->hvirt_cli);
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model_data->hvirt_cli = NULL;
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return errcode;
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}
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return 0;
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}
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void kbase_ipa_detach_vinstr(struct kbase_ipa_model_vinstr_data *model_data)
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{
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if (model_data->hvirt_cli) {
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kbase_hwcnt_virtualizer_client_destroy(model_data->hvirt_cli);
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kbase_hwcnt_dump_buffer_free(&model_data->dump_buf);
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model_data->hvirt_cli = NULL;
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}
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}
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int kbase_ipa_vinstr_dynamic_coeff(struct kbase_ipa_model *model, u32 *coeffp)
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{
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struct kbase_ipa_model_vinstr_data *model_data =
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(struct kbase_ipa_model_vinstr_data *)model->model_data;
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s64 energy = 0;
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size_t i;
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u64 coeff = 0, coeff_mul = 0;
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u64 start_ts_ns, end_ts_ns;
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u32 active_cycles;
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int err = 0;
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err = kbase_hwcnt_virtualizer_client_dump(model_data->hvirt_cli,
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&start_ts_ns, &end_ts_ns, &model_data->dump_buf);
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if (err)
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goto err0;
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/* Range: 0 (GPU not used at all), to the max sampling interval, say
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* 1s, * max GPU frequency (GPU 100% utilized).
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* 0 <= active_cycles <= 1 * ~2GHz
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* 0 <= active_cycles < 2^31
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*/
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active_cycles = model_data->get_active_cycles(model_data);
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if (active_cycles < (u32) max(model_data->min_sample_cycles, 0)) {
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err = -ENODATA;
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goto err0;
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}
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/* Range: 1 <= active_cycles < 2^31 */
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active_cycles = max(1u, active_cycles);
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/* Range of 'energy' is +/- 2^54 * number of IPA groups (~8), so around
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* -2^57 < energy < 2^57
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*/
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for (i = 0; i < model_data->groups_def_num; i++) {
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const struct kbase_ipa_group *group = &model_data->groups_def[i];
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s32 coeff = model_data->group_values[i];
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s64 group_energy = group->op(model_data, coeff,
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group->counter_block_offset);
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energy = kbase_ipa_add_saturate(energy, group_energy);
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}
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/* Range: 0 <= coeff < 2^57 */
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if (energy > 0)
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coeff = energy;
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/* Range: 0 <= coeff < 2^57 (because active_cycles >= 1). However, this
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* can be constrained further: Counter values can only be increased by
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* a theoretical maximum of about 64k per clock cycle. Beyond this,
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* we'd have to sample every 1ms to avoid them overflowing at the
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* lowest clock frequency (say 100MHz). Therefore, we can write the
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* range of 'coeff' in terms of active_cycles:
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*
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* coeff = SUM(coeffN * counterN * num_cores_for_counterN)
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* coeff <= SUM(coeffN * counterN) * max_num_cores
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* coeff <= num_IPA_groups * max_coeff * max_counter * max_num_cores
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* (substitute max_counter = 2^16 * active_cycles)
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* coeff <= num_IPA_groups * max_coeff * 2^16 * active_cycles * max_num_cores
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* coeff <= 2^3 * 2^22 * 2^16 * active_cycles * 2^5
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* coeff <= 2^46 * active_cycles
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*
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* So after the division: 0 <= coeff <= 2^46
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*/
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coeff = div_u64(coeff, active_cycles);
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/* Not all models were derived at the same reference voltage. Voltage
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* scaling is done by multiplying by V^2, so we need to *divide* by
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* Vref^2 here.
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* Range: 0 <= coeff <= 2^49
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*/
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coeff = div_u64(coeff * 1000, max(model_data->reference_voltage, 1));
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/* Range: 0 <= coeff <= 2^52 */
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coeff = div_u64(coeff * 1000, max(model_data->reference_voltage, 1));
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/* Scale by user-specified integer factor.
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* Range: 0 <= coeff_mul < 2^57
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*/
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coeff_mul = coeff * model_data->scaling_factor;
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/* The power models have results with units
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* mW/(MHz V^2), i.e. nW/(Hz V^2). With precision of 1/1000000, this
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* becomes fW/(Hz V^2), which are the units of coeff_mul. However,
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* kbase_scale_dynamic_power() expects units of pW/(Hz V^2), so divide
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* by 1000.
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* Range: 0 <= coeff_mul < 2^47
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*/
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coeff_mul = div_u64(coeff_mul, 1000u);
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err0:
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/* Clamp to a sensible range - 2^16 gives about 14W at 400MHz/750mV */
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*coeffp = clamp(coeff_mul, (u64) 0, (u64) 1 << 16);
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return err;
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}
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void kbase_ipa_vinstr_reset_data(struct kbase_ipa_model *model)
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{
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/* Currently not implemented */
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WARN_ON_ONCE(1);
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}
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int kbase_ipa_vinstr_common_model_init(struct kbase_ipa_model *model,
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const struct kbase_ipa_group *ipa_groups_def,
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size_t ipa_group_size,
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kbase_ipa_get_active_cycles_callback get_active_cycles,
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s32 reference_voltage)
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{
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int err = 0;
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size_t i;
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struct kbase_ipa_model_vinstr_data *model_data;
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if (!model || !ipa_groups_def || !ipa_group_size || !get_active_cycles)
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return -EINVAL;
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model_data = kzalloc(sizeof(*model_data), GFP_KERNEL);
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if (!model_data)
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return -ENOMEM;
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model_data->kbdev = model->kbdev;
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model_data->groups_def = ipa_groups_def;
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model_data->groups_def_num = ipa_group_size;
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model_data->get_active_cycles = get_active_cycles;
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model->model_data = (void *) model_data;
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for (i = 0; i < model_data->groups_def_num; ++i) {
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const struct kbase_ipa_group *group = &model_data->groups_def[i];
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model_data->group_values[i] = group->default_value;
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err = kbase_ipa_model_add_param_s32(model, group->name,
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&model_data->group_values[i],
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1, false);
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if (err)
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goto exit;
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}
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model_data->scaling_factor = DEFAULT_SCALING_FACTOR;
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err = kbase_ipa_model_add_param_s32(model, "scale",
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&model_data->scaling_factor,
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1, false);
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if (err)
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goto exit;
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model_data->min_sample_cycles = DEFAULT_MIN_SAMPLE_CYCLES;
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err = kbase_ipa_model_add_param_s32(model, "min_sample_cycles",
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&model_data->min_sample_cycles,
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1, false);
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if (err)
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goto exit;
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model_data->reference_voltage = reference_voltage;
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err = kbase_ipa_model_add_param_s32(model, "reference_voltage",
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&model_data->reference_voltage,
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1, false);
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if (err)
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goto exit;
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err = kbase_ipa_attach_vinstr(model_data);
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exit:
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if (err) {
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kbase_ipa_model_param_free_all(model);
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kfree(model_data);
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}
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return err;
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}
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void kbase_ipa_vinstr_common_model_term(struct kbase_ipa_model *model)
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{
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struct kbase_ipa_model_vinstr_data *model_data =
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(struct kbase_ipa_model_vinstr_data *)model->model_data;
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kbase_ipa_detach_vinstr(model_data);
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kfree(model_data);
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}
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