// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#include <mali_kbase.h>
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#include <gpu/mali_kbase_gpu_fault.h>
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#include <backend/gpu/mali_kbase_instr_internal.h>
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#include <backend/gpu/mali_kbase_pm_internal.h>
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#include <device/mali_kbase_device.h>
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#include <mali_kbase_reset_gpu.h>
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#include <mmu/mali_kbase_mmu.h>
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/**
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* kbase_report_gpu_fault - Report a GPU fault.
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* @kbdev: Kbase device pointer
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* @multiple: Zero if only GPU_FAULT was raised, non-zero if MULTIPLE_GPU_FAULTS
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* was also set
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*
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* This function is called from the interrupt handler when a GPU fault occurs.
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* It reports the details of the fault using dev_warn().
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*/
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static void kbase_report_gpu_fault(struct kbase_device *kbdev, int multiple)
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{
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u32 status = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTSTATUS));
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u64 address = (u64) kbase_reg_read(kbdev,
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GPU_CONTROL_REG(GPU_FAULTADDRESS_HI)) << 32;
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address |= kbase_reg_read(kbdev,
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GPU_CONTROL_REG(GPU_FAULTADDRESS_LO));
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dev_warn(kbdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx",
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status,
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kbase_gpu_exception_name(status & 0xFF),
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address);
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if (multiple)
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dev_warn(kbdev->dev, "There were multiple GPU faults - some have not been reported\n");
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}
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void kbase_gpu_interrupt(struct kbase_device *kbdev, u32 val)
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{
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KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ, NULL, val);
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if (val & GPU_FAULT)
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kbase_report_gpu_fault(kbdev, val & MULTIPLE_GPU_FAULTS);
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if (val & RESET_COMPLETED)
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kbase_pm_reset_done(kbdev);
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/* Defer clearing CLEAN_CACHES_COMPLETED to kbase_clean_caches_done.
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* We need to acquire hwaccess_lock to avoid a race condition with
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* kbase_gpu_cache_flush_and_busy_wait
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*/
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KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_CLEAR, NULL, val & ~CLEAN_CACHES_COMPLETED);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val & ~CLEAN_CACHES_COMPLETED);
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/* kbase_instr_hwcnt_sample_done frees the HWCNT pipeline to request another
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* sample. Therefore this must be called after clearing the IRQ to avoid a
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* race between clearing and the next sample raising the IRQ again.
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*/
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if (val & PRFCNT_SAMPLE_COMPLETED)
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kbase_instr_hwcnt_sample_done(kbdev);
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/* kbase_pm_check_transitions (called by kbase_pm_power_changed) must
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* be called after the IRQ has been cleared. This is because it might
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* trigger further power transitions and we don't want to miss the
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* interrupt raised to notify us that these further transitions have
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* finished. The same applies to kbase_clean_caches_done() - if another
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* clean was queued, it might trigger another clean, which might
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* generate another interrupt which shouldn't be missed.
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*/
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if (val & CLEAN_CACHES_COMPLETED)
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kbase_clean_caches_done(kbdev);
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if (val & POWER_CHANGED_ALL) {
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kbase_pm_power_changed(kbdev);
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} else if (val & CLEAN_CACHES_COMPLETED) {
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/* If cache line evict messages can be lost when shader cores
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* power down then we need to flush the L2 cache before powering
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* down cores. When the flush completes, the shaders' state
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* machine needs to be re-invoked to proceed with powering down
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* cores.
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*/
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if (kbdev->pm.backend.l2_always_on ||
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kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_TTRX_921))
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kbase_pm_power_changed(kbdev);
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}
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KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_DONE, NULL, val);
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}
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#if IS_ENABLED(CONFIG_MALI_REAL_HW)
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void kbase_reg_write(struct kbase_device *kbdev, u32 offset, u32 value)
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{
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WARN_ON(!kbdev->pm.backend.gpu_powered);
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writel(value, kbdev->reg + offset);
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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if (unlikely(kbdev->io_history.enabled))
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kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset,
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value, 1);
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#endif /* CONFIG_DEBUG_FS */
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dev_dbg(kbdev->dev, "w: reg %08x val %08x", offset, value);
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}
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KBASE_EXPORT_TEST_API(kbase_reg_write);
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u32 kbase_reg_read(struct kbase_device *kbdev, u32 offset)
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{
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u32 val;
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WARN_ON(!kbdev->pm.backend.gpu_powered);
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val = readl(kbdev->reg + offset);
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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if (unlikely(kbdev->io_history.enabled))
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kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset,
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val, 0);
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#endif /* CONFIG_DEBUG_FS */
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dev_dbg(kbdev->dev, "r: reg %08x val %08x", offset, val);
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return val;
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}
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KBASE_EXPORT_TEST_API(kbase_reg_read);
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#endif /* IS_ENABLED(CONFIG_MALI_REAL_HW) */
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