/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <linux/arm-smccc.h>
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#include <linux/linkage.h>
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#include <asm/alternative.h>
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#include <asm/assembler.h>
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#include <asm/el2_setup.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_mmu.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/sysreg.h>
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#include <asm/virt.h>
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.text
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.pushsection .idmap.text, "ax"
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.align 11
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SYM_CODE_START(__kvm_hyp_init)
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ventry __invalid // Synchronous EL2t
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ventry __invalid // IRQ EL2t
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ventry __invalid // FIQ EL2t
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ventry __invalid // Error EL2t
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ventry __invalid // Synchronous EL2h
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ventry __invalid // IRQ EL2h
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ventry __invalid // FIQ EL2h
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ventry __invalid // Error EL2h
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ventry __do_hyp_init // Synchronous 64-bit EL1
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ventry __invalid // IRQ 64-bit EL1
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ventry __invalid // FIQ 64-bit EL1
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ventry __invalid // Error 64-bit EL1
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ventry __invalid // Synchronous 32-bit EL1
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ventry __invalid // IRQ 32-bit EL1
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ventry __invalid // FIQ 32-bit EL1
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ventry __invalid // Error 32-bit EL1
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__invalid:
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b .
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/*
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* Only uses x0..x3 so as to not clobber callee-saved SMCCC registers.
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*
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* x0: SMCCC function ID
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* x1: struct kvm_nvhe_init_params PA
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*/
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__do_hyp_init:
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/* Check for a stub HVC call */
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cmp x0, #HVC_STUB_HCALL_NR
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b.lo __kvm_handle_stub_hvc
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mov x3, #KVM_HOST_SMCCC_FUNC(__kvm_hyp_init)
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cmp x0, x3
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b.eq 1f
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mov x0, #SMCCC_RET_NOT_SUPPORTED
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eret
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1: mov x0, x1
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mov x3, lr
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bl ___kvm_hyp_init // Clobbers x0..x2
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mov lr, x3
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/* Hello, World! */
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mov x0, #SMCCC_RET_SUCCESS
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eret
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SYM_CODE_END(__kvm_hyp_init)
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/*
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* Initialize the hypervisor in EL2.
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*
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* Only uses x0..x2 so as to not clobber callee-saved SMCCC registers
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* and leave x3 for the caller.
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*
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* x0: struct kvm_nvhe_init_params PA
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*/
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SYM_CODE_START_LOCAL(___kvm_hyp_init)
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ldr x1, [x0, #NVHE_INIT_TPIDR_EL2]
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msr tpidr_el2, x1
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ldr x1, [x0, #NVHE_INIT_STACK_HYP_VA]
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mov sp, x1
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ldr x1, [x0, #NVHE_INIT_MAIR_EL2]
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msr mair_el2, x1
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ldr x1, [x0, #NVHE_INIT_HCR_EL2]
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msr hcr_el2, x1
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ldr x1, [x0, #NVHE_INIT_VTTBR]
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msr vttbr_el2, x1
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ldr x1, [x0, #NVHE_INIT_VTCR]
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msr vtcr_el2, x1
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ldr x1, [x0, #NVHE_INIT_PGD_PA]
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phys_to_ttbr x2, x1
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alternative_if ARM64_HAS_CNP
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orr x2, x2, #TTBR_CNP_BIT
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alternative_else_nop_endif
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msr ttbr0_el2, x2
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/*
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* Set the PS bits in TCR_EL2.
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*/
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ldr x0, [x0, #NVHE_INIT_TCR_EL2]
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tcr_compute_pa_size x0, #TCR_EL2_PS_SHIFT, x1, x2
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msr tcr_el2, x0
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isb
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/* Invalidate the stale TLBs from Bootloader */
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tlbi alle2
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tlbi vmalls12e1
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dsb sy
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mov_q x0, INIT_SCTLR_EL2_MMU_ON
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alternative_if ARM64_HAS_ADDRESS_AUTH
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mov_q x1, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | \
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SCTLR_ELx_ENDA | SCTLR_ELx_ENDB)
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orr x0, x0, x1
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alternative_else_nop_endif
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msr sctlr_el2, x0
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isb
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/* Set the host vector */
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ldr x0, =__kvm_hyp_host_vector
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msr vbar_el2, x0
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ret
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SYM_CODE_END(___kvm_hyp_init)
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/*
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* PSCI CPU_ON entry point
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*
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* x0: struct kvm_nvhe_init_params PA
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*/
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SYM_CODE_START(kvm_hyp_cpu_entry)
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mov x1, #1 // is_cpu_on = true
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b __kvm_hyp_init_cpu
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SYM_CODE_END(kvm_hyp_cpu_entry)
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/*
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* PSCI CPU_SUSPEND / SYSTEM_SUSPEND entry point
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*
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* x0: struct kvm_nvhe_init_params PA
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*/
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SYM_CODE_START(kvm_hyp_cpu_resume)
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mov x1, #0 // is_cpu_on = false
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b __kvm_hyp_init_cpu
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SYM_CODE_END(kvm_hyp_cpu_resume)
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/*
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* Common code for CPU entry points. Initializes EL2 state and
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* installs the hypervisor before handing over to a C handler.
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*
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* x0: struct kvm_nvhe_init_params PA
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* x1: bool is_cpu_on
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*/
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SYM_CODE_START_LOCAL(__kvm_hyp_init_cpu)
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mov x28, x0 // Stash arguments
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mov x29, x1
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/* Check that the core was booted in EL2. */
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mrs x0, CurrentEL
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cmp x0, #CurrentEL_EL2
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b.eq 2f
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/* The core booted in EL1. KVM cannot be initialized on it. */
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1: wfe
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wfi
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b 1b
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2: msr SPsel, #1 // We want to use SP_EL{1,2}
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/* Initialize EL2 CPU state to sane values. */
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init_el2_state // Clobbers x0..x2
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/* Enable MMU, set vectors and stack. */
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mov x0, x28
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bl ___kvm_hyp_init // Clobbers x0..x2
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/* Leave idmap. */
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mov x0, x29
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ldr x1, =kvm_host_psci_cpu_entry
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br x1
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SYM_CODE_END(__kvm_hyp_init_cpu)
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SYM_CODE_START(__kvm_handle_stub_hvc)
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cmp x0, #HVC_SOFT_RESTART
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b.ne 1f
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/* This is where we're about to jump, staying at EL2 */
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msr elr_el2, x1
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mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT | PSR_MODE_EL2h)
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msr spsr_el2, x0
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/* Shuffle the arguments, and don't come back */
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mov x0, x2
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mov x1, x3
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mov x2, x4
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b reset
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1: cmp x0, #HVC_RESET_VECTORS
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b.ne 1f
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/*
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* Set the HVC_RESET_VECTORS return code before entering the common
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* path so that we do not clobber x0-x2 in case we are coming via
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* HVC_SOFT_RESTART.
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*/
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mov x0, xzr
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reset:
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/* Reset kvm back to the hyp stub. */
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mov_q x5, INIT_SCTLR_EL2_MMU_OFF
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pre_disable_mmu_workaround
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msr sctlr_el2, x5
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isb
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alternative_if ARM64_KVM_PROTECTED_MODE
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mov_q x5, HCR_HOST_NVHE_FLAGS
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msr hcr_el2, x5
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alternative_else_nop_endif
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/* Install stub vectors */
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adr_l x5, __hyp_stub_vectors
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msr vbar_el2, x5
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eret
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1: /* Bad stub call */
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mov_q x0, HVC_STUB_ERR
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eret
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SYM_CODE_END(__kvm_handle_stub_hvc)
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SYM_FUNC_START(__pkvm_init_switch_pgd)
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/* Turn the MMU off */
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pre_disable_mmu_workaround
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mrs x2, sctlr_el2
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bic x3, x2, #SCTLR_ELx_M
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msr sctlr_el2, x3
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isb
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tlbi alle2
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/* Install the new pgtables */
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ldr x3, [x0, #NVHE_INIT_PGD_PA]
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phys_to_ttbr x4, x3
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alternative_if ARM64_HAS_CNP
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orr x4, x4, #TTBR_CNP_BIT
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alternative_else_nop_endif
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msr ttbr0_el2, x4
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/* Set the new stack pointer */
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ldr x0, [x0, #NVHE_INIT_STACK_HYP_VA]
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mov sp, x0
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/* And turn the MMU back on! */
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set_sctlr_el2 x2
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ret x1
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SYM_FUNC_END(__pkvm_init_switch_pgd)
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.popsection
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