// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/clock/rk3568-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/rk3568-power.h>
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#include <dt-bindings/soc/rockchip-system-status.h>
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#include <dt-bindings/suspend/rockchip-rk3568.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "rk3568-dram-default-timing.dtsi"
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/ {
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compatible = "rockchip,rk3568";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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csi2dphy0 = &csi2_dphy0;
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csi2dphy1 = &csi2_dphy1;
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csi2dphy2 = &csi2_dphy2;
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dsi0 = &dsi0;
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dsi1 = &dsi1;
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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gpio4 = &gpio4;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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mmc0 = &sdhci;
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mmc1 = &sdmmc0;
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mmc2 = &sdmmc1;
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mmc3 = &sdmmc2;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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serial6 = &uart6;
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serial7 = &uart7;
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serial8 = &uart8;
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serial9 = &uart9;
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spi0 = &spi0;
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spi1 = &spi1;
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spi2 = &spi2;
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spi3 = &spi3;
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lvds0 = &lvds;
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lvds1 = &lvds1;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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clocks = <&scmi_clk 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP>;
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#cooling-cells = <2>;
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dynamic-power-coefficient = <187>;
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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clocks = <&scmi_clk 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "psci";
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clocks = <&scmi_clk 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP>;
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "psci";
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clocks = <&scmi_clk 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP>;
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP: cpu-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <100>;
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exit-latency-us = <120>;
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min-residency-us = <1000>;
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};
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};
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};
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cpu0_opp_table: cpu0-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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mbist-vmin = <825000 900000 950000>;
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nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>,
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<&specification_serial_number>, <&remark_spec_serial_number>;
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nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
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"specification_serial_number", "remark_spec_serial_number";
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rockchip,supported-hw;
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rockchip,max-volt = <1150000>;
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rockchip,pvtm-voltage-sel = <
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0 84000 0
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84001 87000 1
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87001 91000 2
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91001 100000 3
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>;
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rockchip,pvtm-freq = <408000>;
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rockchip,pvtm-volt = <900000>;
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rockchip,pvtm-ch = <0 5>;
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rockchip,pvtm-sample-time = <1000>;
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rockchip,pvtm-number = <10>;
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rockchip,pvtm-error = <1000>;
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rockchip,pvtm-ref-temp = <40>;
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rockchip,pvtm-temp-prop = <26 26>;
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rockchip,thermal-zone = "soc-thermal";
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rockchip,temp-hysteresis = <5000>;
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rockchip,low-temp = <0>;
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rockchip,low-temp-adjust-volt = <
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/* MHz MHz uV */
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0 1992 75000
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>;
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/* RK3568 && RK3568M cpu OPPs */
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opp-408000000 {
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opp-supported-hw = <0xfb 0xffff>;
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <850000 850000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-600000000 {
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opp-supported-hw = <0xfb 0xffff>;
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <850000 850000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-816000000 {
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opp-supported-hw = <0xfb 0xffff>;
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <850000 850000 1150000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-1104000000 {
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opp-supported-hw = <0xfb 0xffff>;
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opp-hz = /bits/ 64 <1104000000>;
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opp-microvolt = <900000 900000 1150000>;
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opp-microvolt-L0 = <900000 900000 1150000>;
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opp-microvolt-L1 = <850000 850000 1150000>;
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opp-microvolt-L2 = <850000 850000 1150000>;
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opp-microvolt-L3 = <850000 850000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-1416000000 {
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opp-supported-hw = <0xfb 0xffff>;
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <1025000 1025000 1150000>;
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opp-microvolt-L0 = <1025000 1025000 1150000>;
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opp-microvolt-L1 = <975000 975000 1150000>;
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opp-microvolt-L2 = <950000 950000 1150000>;
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opp-microvolt-L3 = <925000 925000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-1608000000 {
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opp-supported-hw = <0xf9 0xffff>;
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <1100000 1100000 1150000>;
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opp-microvolt-L0 = <1100000 1100000 1150000>;
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opp-microvolt-L1 = <1050000 1050000 1150000>;
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opp-microvolt-L2 = <1025000 1025000 1150000>;
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opp-microvolt-L3 = <1000000 1000000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-1800000000 {
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opp-supported-hw = <0xf9 0xffff>;
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1150000 1150000 1150000>;
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opp-microvolt-L0 = <1150000 1150000 1150000>;
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opp-microvolt-L1 = <1100000 1100000 1150000>;
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opp-microvolt-L2 = <1075000 1075000 1150000>;
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opp-microvolt-L3 = <1050000 1050000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-1992000000 {
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opp-supported-hw = <0xf9 0xffff>;
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opp-hz = /bits/ 64 <1992000000>;
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opp-microvolt = <1150000 1150000 1150000>;
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opp-microvolt-L0 = <1150000 1150000 1150000>;
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opp-microvolt-L1 = <1150000 1150000 1150000>;
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opp-microvolt-L2 = <1125000 1125000 1150000>;
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opp-microvolt-L3 = <1100000 1100000 1150000>;
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clock-latency-ns = <40000>;
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};
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/* RK3568J cpu OPPs */
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opp-j-1008000000 {
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opp-supported-hw = <0x04 0xffff>;
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <850000 850000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-j-1416000000 {
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opp-supported-hw = <0x04 0xffff>;
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <900000 900000 1150000>;
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clock-latency-ns = <40000>;
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};
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/* RK3568M cpu OPPs */
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opp-m-1608000000 {
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opp-supported-hw = <0x02 0xffff>;
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <1000000 1000000 1150000>;
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clock-latency-ns = <40000>;
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};
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};
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arm_pmu: arm-pmu {
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compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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cpuinfo {
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compatible = "rockchip,cpuinfo";
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nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
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nvmem-cell-names = "id", "cpu-version", "cpu-code";
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};
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display_subsystem: display-subsystem {
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compatible = "rockchip,display-subsystem";
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memory-region = <&drm_logo>, <&drm_cubic_lut>;
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memory-region-names = "drm-logo", "drm-cubic-lut";
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ports = <&vop_out>;
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devfreq = <&dmc>;
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route {
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route_dsi0: route-dsi0 {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vp0_out_dsi0>;
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};
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route_dsi1: route-dsi1 {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vp1_out_dsi1>;
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};
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route_edp: route-edp {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vp1_out_edp>;
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};
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route_hdmi: route-hdmi {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vp0_out_hdmi>;
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};
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route_lvds: route-lvds {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vp1_out_lvds>;
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};
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route_rgb: route-rgb {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vp2_out_rgb>;
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};
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};
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};
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edac: edac {
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compatible = "rockchip,rk3568-edac";
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interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ce", "ue";
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status = "disabled";
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};
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firmware {
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scmi: scmi {
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compatible = "arm,scmi-smc";
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shmem = <&scmi_shmem>;
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arm,smc-id = <0x82000010>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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rockchip,clk-init = <1104000000>;
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};
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};
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sdei: sdei {
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compatible = "arm,sdei-1.0";
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method = "smc";
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};
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};
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mipi_csi2: mipi-csi2 {
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compatible = "rockchip,rk3568-mipi-csi2";
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rockchip,hw = <&mipi_csi2_hw>;
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status = "disabled";
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};
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mpp_srv: mpp-srv {
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compatible = "rockchip,mpp-service";
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rockchip,taskqueue-count = <6>;
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rockchip,resetgroup-count = <6>;
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status = "disabled";
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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drm_logo: drm-logo@00000000 {
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compatible = "rockchip,drm-logo";
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reg = <0x0 0x0 0x0 0x0>;
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};
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drm_cubic_lut: drm-cubic-lut@00000000 {
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compatible = "rockchip,drm-cubic-lut";
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reg = <0x0 0x0 0x0 0x0>;
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};
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};
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rockchip_suspend: rockchip-suspend {
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compatible = "rockchip,pm-rk3568";
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status = "disabled";
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rockchip,sleep-debug-en = <1>;
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rockchip,sleep-mode-config = <
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(0
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| RKPM_SLP_ARMOFF_LOGOFF
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| RKPM_SLP_CENTER_OFF
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| RKPM_SLP_HW_PLLS_OFF
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| RKPM_SLP_PMUALIVE_32K
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| RKPM_SLP_OSC_DIS
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| RKPM_SLP_PMIC_LP
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| RKPM_SLP_32K_PVTM
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)
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>;
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rockchip,wakeup-config = <
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(0
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| RKPM_GPIO_WKUP_EN
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)
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>;
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};
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rockchip_system_monitor: rockchip-system-monitor {
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compatible = "rockchip,system-monitor";
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rockchip,thermal-zone = "soc-thermal";
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};
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thermal_zones: thermal-zones {
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soc_thermal: soc-thermal {
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polling-delay-passive = <20>; /* milliseconds */
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polling-delay = <1000>; /* milliseconds */
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sustainable-power = <905>; /* milliwatts */
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thermal-sensors = <&tsadc 0>;
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trips {
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threshold: trip-point-0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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target: trip-point-1 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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soc_crit: soc-crit {
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/* millicelsius */
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temperature = <115000>;
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/* millicelsius */
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&target>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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contribution = <1024>;
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};
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map1 {
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trip = <&target>;
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cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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contribution = <1024>;
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};
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};
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};
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gpu_thermal: gpu-thermal {
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polling-delay-passive = <20>; /* milliseconds */
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polling-delay = <1000>; /* milliseconds */
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thermal-sensors = <&tsadc 1>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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arm,no-tick-in-suspend;
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};
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gmac0_clkin: external-gmac0-clock {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "gmac0_clkin";
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#clock-cells = <0>;
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};
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gmac1_clkin: external-gmac1-clock {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "gmac1_clkin";
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#clock-cells = <0>;
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};
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gmac0_xpcsclk: xpcs-gmac0-clock {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "clk_gmac0_xpcs_mii";
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#clock-cells = <0>;
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};
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gmac1_xpcsclk: xpcs-gmac1-clock {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "clk_gmac1_xpcs_mii";
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#clock-cells = <0>;
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};
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i2s1_mclkin_rx: i2s1-mclkin-rx {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12288000>;
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clock-output-names = "i2s1_mclkin_rx";
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};
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i2s1_mclkin_tx: i2s1-mclkin-tx {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12288000>;
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clock-output-names = "i2s1_mclkin_tx";
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};
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i2s2_mclkin: i2s2-mclkin {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12288000>;
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clock-output-names = "i2s2_mclkin";
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};
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|
i2s3_mclkin: i2s3-mclkin {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12288000>;
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clock-output-names = "i2s3_mclkin";
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};
|
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mpll: mpll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <800000000>;
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clock-output-names = "mpll";
|
};
|
|
xin24m: xin24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
|
clock-output-names = "xin24m";
|
};
|
|
xin32k: xin32k {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "xin32k";
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#clock-cells = <0>;
|
pinctrl-names = "default";
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pinctrl-0 = <&clk32k_out0>;
|
};
|
|
scmi_shmem: scmi-shmem@10f000 {
|
compatible = "arm,scmi-shmem";
|
reg = <0x0 0x0010f000 0x0 0x100>;
|
};
|
|
sata0: sata@fc000000 {
|
compatible = "snps,dwc-ahci";
|
reg = <0 0xfc000000 0 0x1000>;
|
clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
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<&cru CLK_SATA0_RXOOB>;
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clock-names = "sata", "pmalive", "rxoob";
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "hostc";
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phys = <&combphy0_us PHY_TYPE_SATA>;
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phy-names = "sata-phy";
|
ports-implemented = <0x1>;
|
power-domains = <&power RK3568_PD_PIPE>;
|
status = "disabled";
|
};
|
|
sata1: sata@fc400000 {
|
compatible = "snps,dwc-ahci";
|
reg = <0 0xfc400000 0 0x1000>;
|
clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
|
<&cru CLK_SATA1_RXOOB>;
|
clock-names = "sata", "pmalive", "rxoob";
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "hostc";
|
phys = <&combphy1_usq PHY_TYPE_SATA>;
|
phy-names = "sata-phy";
|
ports-implemented = <0x1>;
|
power-domains = <&power RK3568_PD_PIPE>;
|
status = "disabled";
|
};
|
|
sata2: sata@fc800000 {
|
compatible = "snps,dwc-ahci";
|
reg = <0 0xfc800000 0 0x1000>;
|
clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
|
<&cru CLK_SATA2_RXOOB>;
|
clock-names = "sata", "pmalive", "rxoob";
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "hostc";
|
phys = <&combphy2_psq PHY_TYPE_SATA>;
|
phy-names = "sata-phy";
|
ports-implemented = <0x1>;
|
power-domains = <&power RK3568_PD_PIPE>;
|
status = "disabled";
|
};
|
|
usbdrd30: usbdrd {
|
compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
|
clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
|
<&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>;
|
clock-names = "ref_clk", "suspend_clk",
|
"bus_clk", "pipe_clk";
|
#address-cells = <2>;
|
#size-cells = <2>;
|
ranges;
|
status = "disabled";
|
|
usbdrd_dwc3: dwc3@fcc00000 {
|
compatible = "snps,dwc3";
|
reg = <0x0 0xfcc00000 0x0 0x400000>;
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
dr_mode = "otg";
|
phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>;
|
phy-names = "usb2-phy", "usb3-phy";
|
phy_type = "utmi_wide";
|
power-domains = <&power RK3568_PD_PIPE>;
|
resets = <&cru SRST_USB3OTG0>;
|
reset-names = "usb3-otg";
|
snps,dis_enblslpm_quirk;
|
snps,dis-u1-entry-quirk;
|
snps,dis-u2-entry-quirk;
|
snps,dis-u2-freeclk-exists-quirk;
|
snps,dis-del-phy-power-chg-quirk;
|
snps,dis-tx-ipgap-linecheck-quirk;
|
snps,dis_rxdet_inp3_quirk;
|
snps,xhci-trb-ent-quirk;
|
snps,parkmode-disable-hs-quirk;
|
snps,parkmode-disable-ss-quirk;
|
quirk-skip-phy-init;
|
status = "disabled";
|
};
|
};
|
|
usbhost30: usbhost {
|
compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
|
clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
|
<&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>;
|
clock-names = "ref_clk", "suspend_clk",
|
"bus_clk", "pipe_clk";
|
#address-cells = <2>;
|
#size-cells = <2>;
|
ranges;
|
status = "disabled";
|
|
usbhost_dwc3: dwc3@fd000000 {
|
compatible = "snps,dwc3";
|
reg = <0x0 0xfd000000 0x0 0x400000>;
|
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
dr_mode = "host";
|
phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>;
|
phy-names = "usb2-phy", "usb3-phy";
|
phy_type = "utmi_wide";
|
power-domains = <&power RK3568_PD_PIPE>;
|
resets = <&cru SRST_USB3OTG1>;
|
reset-names = "usb3-host";
|
snps,dis_enblslpm_quirk;
|
snps,dis-u2-freeclk-exists-quirk;
|
snps,dis-del-phy-power-chg-quirk;
|
snps,dis-tx-ipgap-linecheck-quirk;
|
snps,dis_rxdet_inp3_quirk;
|
snps,xhci-trb-ent-quirk;
|
snps,parkmode-disable-hs-quirk;
|
snps,parkmode-disable-ss-quirk;
|
status = "disabled";
|
};
|
};
|
|
gic: interrupt-controller@fd400000 {
|
compatible = "arm,gic-v3";
|
#interrupt-cells = <3>;
|
#address-cells = <2>;
|
#size-cells = <2>;
|
ranges;
|
interrupt-controller;
|
|
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
<0x0 0xfd460000 0 0xc0000>; /* GICR */
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
its: interrupt-controller@fd440000 {
|
compatible = "arm,gic-v3-its";
|
msi-controller;
|
#msi-cells = <1>;
|
reg = <0x0 0xfd440000 0x0 0x20000>;
|
};
|
};
|
|
usb_host0_ehci: usb@fd800000 {
|
compatible = "generic-ehci";
|
reg = <0x0 0xfd800000 0x0 0x40000>;
|
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
|
<&cru PCLK_USB>, <&usb2phy1>;
|
clock-names = "usbhost", "arbiter", "pclk", "utmi";
|
phys = <&u2phy1_otg>;
|
phy-names = "usb2-phy";
|
status = "disabled";
|
};
|
|
usb_host0_ohci: usb@fd840000 {
|
compatible = "generic-ohci";
|
reg = <0x0 0xfd840000 0x0 0x40000>;
|
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
|
<&cru PCLK_USB>, <&usb2phy1>;
|
clock-names = "usbhost", "arbiter", "pclk", "utmi";
|
phys = <&u2phy1_otg>;
|
phy-names = "usb2-phy";
|
status = "disabled";
|
};
|
|
usb_host1_ehci: usb@fd880000 {
|
compatible = "generic-ehci";
|
reg = <0x0 0xfd880000 0x0 0x40000>;
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
|
<&cru PCLK_USB>, <&usb2phy1>;
|
clock-names = "usbhost", "arbiter", "pclk", "utmi";
|
phys = <&u2phy1_host>;
|
phy-names = "usb2-phy";
|
status = "disabled";
|
};
|
|
usb_host1_ohci: usb@fd8c0000 {
|
compatible = "generic-ohci";
|
reg = <0x0 0xfd8c0000 0x0 0x40000>;
|
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
|
<&cru PCLK_USB>, <&usb2phy1>;
|
clock-names = "usbhost", "arbiter", "pclk", "utmi";
|
phys = <&u2phy1_host>;
|
phy-names = "usb2-phy";
|
status = "disabled";
|
};
|
|
xpcs: syscon@fda00000 {
|
compatible = "rockchip,rk3568-xpcs", "syscon";
|
reg = <0x0 0xfda00000 0x0 0x200000>;
|
status = "disabled";
|
};
|
|
pmugrf: syscon@fdc20000 {
|
compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
|
reg = <0x0 0xfdc20000 0x0 0x10000>;
|
|
pmu_io_domains: io-domains {
|
compatible = "rockchip,rk3568-pmu-io-voltage-domain";
|
status = "disabled";
|
};
|
|
reboot_mode: reboot-mode {
|
compatible = "syscon-reboot-mode";
|
offset = <0x200>;
|
mode-bootloader = <BOOT_BL_DOWNLOAD>;
|
mode-charge = <BOOT_CHARGING>;
|
mode-fastboot = <BOOT_FASTBOOT>;
|
mode-loader = <BOOT_BL_DOWNLOAD>;
|
mode-normal = <BOOT_NORMAL>;
|
mode-recovery = <BOOT_RECOVERY>;
|
mode-ums = <BOOT_UMS>;
|
mode-panic = <BOOT_PANIC>;
|
mode-watchdog = <BOOT_WATCHDOG>;
|
};
|
};
|
|
pipegrf: syscon@fdc50000 {
|
compatible = "rockchip,rk3568-pipegrf", "syscon";
|
reg = <0x0 0xfdc50000 0x0 0x1000>;
|
};
|
|
grf: syscon@fdc60000 {
|
compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
|
reg = <0x0 0xfdc60000 0x0 0x10000>;
|
|
io_domains: io-domains {
|
compatible = "rockchip,rk3568-io-voltage-domain";
|
status = "disabled";
|
};
|
|
lvds: lvds {
|
compatible = "rockchip,rk3568-lvds";
|
phys = <&video_phy0>;
|
phy-names = "phy";
|
status = "disabled";
|
|
ports {
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
port@0 {
|
reg = <0>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
lvds_in_vp1: endpoint@1 {
|
reg = <1>;
|
remote-endpoint = <&vp1_out_lvds>;
|
status = "disabled";
|
};
|
|
lvds_in_vp2: endpoint@2 {
|
reg = <2>;
|
remote-endpoint = <&vp2_out_lvds>;
|
status = "disabled";
|
};
|
};
|
};
|
};
|
|
lvds1: lvds1 {
|
compatible = "rockchip,rk3568-lvds";
|
phys = <&video_phy1>;
|
phy-names = "phy";
|
status = "disabled";
|
|
ports {
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
port@0 {
|
reg = <0>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
lvds1_in_vp1: endpoint@0 {
|
reg = <0>;
|
remote-endpoint = <&vp1_out_lvds1>;
|
};
|
|
lvds1_in_vp2: endpoint@1 {
|
reg = <1>;
|
remote-endpoint = <&vp2_out_lvds1>;
|
};
|
};
|
};
|
};
|
|
rgb: rgb {
|
compatible = "rockchip,rk3568-rgb";
|
pinctrl-names = "default";
|
pinctrl-0 = <&lcdc_ctl>;
|
status = "disabled";
|
|
ports {
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
port@0 {
|
reg = <0>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
rgb_in_vp2: endpoint@2 {
|
reg = <2>;
|
remote-endpoint = <&vp2_out_rgb>;
|
status = "disabled";
|
};
|
};
|
};
|
};
|
|
};
|
|
pipe_phy_grf0: syscon@fdc70000 {
|
compatible = "rockchip,pipe-phy-grf", "syscon";
|
reg = <0x0 0xfdc70000 0x0 0x1000>;
|
};
|
|
pipe_phy_grf1: syscon@fdc80000 {
|
compatible = "rockchip,pipe-phy-grf", "syscon";
|
reg = <0x0 0xfdc80000 0x0 0x1000>;
|
};
|
|
pipe_phy_grf2: syscon@fdc90000 {
|
compatible = "rockchip,pipe-phy-grf", "syscon";
|
reg = <0x0 0xfdc90000 0x0 0x1000>;
|
};
|
|
usb2phy0_grf: syscon@fdca0000 {
|
compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
|
reg = <0x0 0xfdca0000 0x0 0x8000>;
|
};
|
|
usb2phy1_grf: syscon@fdca8000 {
|
compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
|
reg = <0x0 0xfdca8000 0x0 0x8000>;
|
};
|
|
edp_phy_grf: syscon@fdcb0000 {
|
compatible = "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd";
|
reg = <0x0 0xfdcb0000 0x0 0x100>;
|
clocks = <&cru PCLK_EDPPHY_GRF>;
|
|
edp_phy: edp-phy {
|
compatible = "rockchip,rk3568-edp-phy";
|
clocks = <&pmucru XIN_OSC0_EDPPHY_G>;
|
clock-names = "refclk";
|
#phy-cells = <0>;
|
status = "disabled";
|
};
|
};
|
|
pcie30_phy_grf: syscon@fdcb8000 {
|
compatible = "rockchip,pcie30-phy-grf", "syscon";
|
reg = <0x0 0xfdcb8000 0x0 0x10000>;
|
};
|
|
sram: sram@fdcc0000 {
|
compatible = "mmio-sram";
|
reg = <0x0 0xfdcc0000 0x0 0xb000>;
|
|
#address-cells = <1>;
|
#size-cells = <1>;
|
ranges = <0x0 0x0 0xfdcc0000 0xb000>;
|
|
/* start address and size should be 4k algin */
|
rkvdec_sram: rkvdec-sram@0 {
|
reg = <0x0 0xb000>;
|
};
|
};
|
|
pmucru: clock-controller@fdd00000 {
|
compatible = "rockchip,rk3568-pmucru";
|
reg = <0x0 0xfdd00000 0x0 0x1000>;
|
rockchip,grf = <&grf>;
|
rockchip,pmugrf = <&pmugrf>;
|
#clock-cells = <1>;
|
#reset-cells = <1>;
|
|
assigned-clocks = <&pmucru SCLK_32K_IOE>;
|
assigned-clock-parents = <&pmucru CLK_RTC_32K>;
|
};
|
|
cru: clock-controller@fdd20000 {
|
compatible = "rockchip,rk3568-cru";
|
reg = <0x0 0xfdd20000 0x0 0x1000>;
|
rockchip,grf = <&grf>;
|
#clock-cells = <1>;
|
#reset-cells = <1>;
|
|
assigned-clocks =
|
<&pmucru CLK_RTC_32K>, <&cru ACLK_RKVDEC_PRE>,
|
<&cru CLK_RKVDEC_CORE>, <&pmucru PLL_PPLL>,
|
<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
|
<&cru CPLL_500M>, <&cru CPLL_333M>,
|
<&cru CPLL_250M>, <&cru CPLL_125M>,
|
<&cru CPLL_100M>, <&cru CPLL_62P5M>,
|
<&cru CPLL_50M>, <&cru CPLL_25M>,
|
<&cru PLL_GPLL>,
|
<&cru ACLK_BUS>, <&cru PCLK_BUS>,
|
<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
|
<&cru HCLK_TOP>, <&cru PCLK_TOP>,
|
<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
|
<&cru PLL_NPLL>, <&cru ACLK_PIPE>,
|
<&cru PCLK_PIPE>, <&cru CLK_I2S0_8CH_TX_SRC>,
|
<&cru CLK_I2S0_8CH_RX_SRC>, <&cru CLK_I2S1_8CH_TX_SRC>,
|
<&cru CLK_I2S1_8CH_RX_SRC>, <&cru CLK_I2S2_2CH_SRC>,
|
<&cru CLK_I2S2_2CH_SRC>, <&cru CLK_I2S3_2CH_RX_SRC>,
|
<&cru CLK_I2S3_2CH_TX_SRC>, <&cru MCLK_SPDIF_8CH_SRC>,
|
<&cru ACLK_VOP>;
|
assigned-clock-rates =
|
<32768>, <300000000>,
|
<300000000>, <200000000>,
|
<100000000>, <1000000000>,
|
<500000000>, <333000000>,
|
<250000000>, <125000000>,
|
<100000000>, <62500000>,
|
<50000000>, <25000000>,
|
<1188000000>,
|
<150000000>, <100000000>,
|
<500000000>, <400000000>,
|
<150000000>, <100000000>,
|
<300000000>, <150000000>,
|
<1200000000>, <400000000>,
|
<100000000>, <1188000000>,
|
<1188000000>, <1188000000>,
|
<1188000000>, <1188000000>,
|
<1188000000>, <1188000000>,
|
<1188000000>, <1188000000>,
|
<500000000>;
|
assigned-clock-parents =
|
<&pmucru CLK_RTC32K_FRAC>, <&cru PLL_GPLL>,
|
<&cru PLL_GPLL>;
|
};
|
|
i2c0: i2c@fdd40000 {
|
compatible = "rockchip,rk3399-i2c";
|
reg = <0x0 0xfdd40000 0x0 0x1000>;
|
clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
|
clock-names = "i2c", "pclk";
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&i2c0_xfer>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
status = "disabled";
|
};
|
|
uart0: serial@fdd50000 {
|
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfdd50000 0x0 0x100>;
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <2>;
|
reg-io-width = <4>;
|
dmas = <&dmac0 0>, <&dmac0 1>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&uart0_xfer>;
|
status = "disabled";
|
};
|
|
pwm0: pwm@fdd70000 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfdd70000 0x0 0x10>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm0m0_pins>;
|
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm1: pwm@fdd70010 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfdd70010 0x0 0x10>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm1m0_pins>;
|
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm2: pwm@fdd70020 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfdd70020 0x0 0x10>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm2m0_pins>;
|
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm3: pwm@fdd70030 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfdd70030 0x0 0x10>;
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm3_pins>;
|
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pmu: power-management@fdd90000 {
|
compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
|
reg = <0x0 0xfdd90000 0x0 0x1000>;
|
|
power: power-controller {
|
compatible = "rockchip,rk3568-power-controller";
|
#power-domain-cells = <1>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
status = "okay";
|
|
/* These power domains are grouped by VD_NPU */
|
pd_npu@RK3568_PD_NPU {
|
reg = <RK3568_PD_NPU>;
|
clocks = <&cru ACLK_NPU_PRE>,
|
<&cru HCLK_NPU_PRE>,
|
<&cru PCLK_NPU_PRE>;
|
pm_qos = <&qos_npu>;
|
};
|
/* These power domains are grouped by VD_GPU */
|
pd_gpu@RK3568_PD_GPU {
|
reg = <RK3568_PD_GPU>;
|
clocks = <&cru ACLK_GPU_PRE>,
|
<&cru PCLK_GPU_PRE>;
|
pm_qos = <&qos_gpu>;
|
};
|
/* These power domains are grouped by VD_LOGIC */
|
pd_vi@RK3568_PD_VI {
|
reg = <RK3568_PD_VI>;
|
clocks = <&cru HCLK_VI>,
|
<&cru PCLK_VI>;
|
pm_qos = <&qos_isp>,
|
<&qos_vicap0>,
|
<&qos_vicap1>;
|
};
|
pd_vo@RK3568_PD_VO {
|
reg = <RK3568_PD_VO>;
|
clocks = <&cru HCLK_VO>,
|
<&cru PCLK_VO>,
|
<&cru ACLK_VOP_PRE>;
|
pm_qos = <&qos_hdcp>,
|
<&qos_vop_m0>,
|
<&qos_vop_m1>;
|
};
|
pd_rga@RK3568_PD_RGA {
|
reg = <RK3568_PD_RGA>;
|
clocks = <&cru HCLK_RGA_PRE>,
|
<&cru PCLK_RGA_PRE>;
|
pm_qos = <&qos_ebc>,
|
<&qos_iep>,
|
<&qos_jpeg_dec>,
|
<&qos_jpeg_enc>,
|
<&qos_rga_rd>,
|
<&qos_rga_wr>;
|
};
|
pd_vpu@RK3568_PD_VPU {
|
reg = <RK3568_PD_VPU>;
|
clocks = <&cru HCLK_VPU_PRE>;
|
pm_qos = <&qos_vpu>;
|
};
|
pd_rkvdec@RK3568_PD_RKVDEC {
|
clocks = <&cru HCLK_RKVDEC_PRE>;
|
reg = <RK3568_PD_RKVDEC>;
|
pm_qos = <&qos_rkvdec>;
|
};
|
pd_rkvenc@RK3568_PD_RKVENC {
|
reg = <RK3568_PD_RKVENC>;
|
clocks = <&cru HCLK_RKVENC_PRE>;
|
pm_qos = <&qos_rkvenc_rd_m0>,
|
<&qos_rkvenc_rd_m1>,
|
<&qos_rkvenc_wr_m0>;
|
};
|
pd_pipe@RK3568_PD_PIPE {
|
reg = <RK3568_PD_PIPE>;
|
clocks = <&cru PCLK_PIPE>;
|
pm_qos = <&qos_pcie2x1>,
|
<&qos_pcie3x1>,
|
<&qos_pcie3x2>,
|
<&qos_sata0>,
|
<&qos_sata1>,
|
<&qos_sata2>,
|
<&qos_usb3_0>,
|
<&qos_usb3_1>;
|
};
|
};
|
};
|
|
pvtm@fde00000 {
|
compatible = "rockchip,rk3568-core-pvtm";
|
reg = <0x0 0xfde00000 0x0 0x100>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
pvtm@0 {
|
reg = <0>;
|
clocks = <&cru CLK_CORE_PVTM>, <&cru PCLK_CORE_PVTM>;
|
clock-names = "clk", "pclk";
|
resets = <&cru SRST_CORE_PVTM>, <&cru SRST_P_CORE_PVTM>;
|
reset-names = "rts", "rst-p";
|
thermal-zone = "soc-thermal";
|
};
|
};
|
|
rknpu: npu@fde40000 {
|
compatible = "rockchip,rk3568-rknpu", "rockchip,rknpu";
|
reg = <0x0 0xfde40000 0x0 0x10000>;
|
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&scmi_clk 2>, <&cru CLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>;
|
clock-names = "scmi_clk", "clk", "aclk", "hclk";
|
assigned-clocks = <&cru CLK_NPU>;
|
assigned-clock-rates = <600000000>;
|
resets = <&cru SRST_A_NPU>, <&cru SRST_H_NPU>;
|
reset-names = "srst_a", "srst_h";
|
power-domains = <&power RK3568_PD_NPU>;
|
operating-points-v2 = <&npu_opp_table>;
|
iommus = <&rknpu_mmu>;
|
status = "disabled";
|
};
|
|
npu_opp_table: npu-opp-table {
|
compatible = "operating-points-v2";
|
|
mbist-vmin = <825000 900000 950000>;
|
nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>,
|
<&specification_serial_number>, <&remark_spec_serial_number>;
|
nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
|
"specification_serial_number", "remark_spec_serial_number";
|
rockchip,supported-hw;
|
rockchip,max-volt = <1000000>;
|
rockchip,temp-hysteresis = <5000>;
|
rockchip,low-temp = <0>;
|
rockchip,low-temp-adjust-volt = <
|
/* MHz MHz uV */
|
0 1000 50000
|
>;
|
rockchip,pvtm-voltage-sel = <
|
0 84000 0
|
84001 87000 1
|
87001 91000 2
|
91001 100000 3
|
>;
|
rockchip,pvtm-ch = <0 5>;
|
|
/* RK3568 && RK3568M npu OPPs */
|
opp-200000000 {
|
opp-supported-hw = <0xfb 0xffff>;
|
opp-hz = /bits/ 64 <200000000>;
|
opp-microvolt = <850000 850000 1000000>;
|
};
|
opp-300000000 {
|
opp-supported-hw = <0xfb 0xffff>;
|
opp-hz = /bits/ 64 <297000000>;
|
opp-microvolt = <850000 850000 1000000>;
|
};
|
opp-400000000 {
|
opp-supported-hw = <0xfb 0xffff>;
|
opp-hz = /bits/ 64 <400000000>;
|
opp-microvolt = <850000 850000 1000000>;
|
};
|
opp-600000000 {
|
opp-supported-hw = <0xfb 0xffff>;
|
opp-hz = /bits/ 64 <600000000>;
|
opp-microvolt = <850000 850000 1000000>;
|
};
|
opp-700000000 {
|
opp-supported-hw = <0xfb 0xffff>;
|
opp-hz = /bits/ 64 <700000000>;
|
opp-microvolt = <875000 875000 1000000>;
|
opp-microvolt-L0 = <875000 875000 1000000>;
|
opp-microvolt-L1 = <850000 850000 1000000>;
|
opp-microvolt-L2 = <850000 850000 1000000>;
|
opp-microvolt-L3 = <850000 850000 1000000>;
|
};
|
opp-800000000 {
|
opp-supported-hw = <0xfb 0xffff>;
|
opp-hz = /bits/ 64 <800000000>;
|
opp-microvolt = <925000 925000 1000000>;
|
opp-microvolt-L0 = <925000 925000 1000000>;
|
opp-microvolt-L1 = <900000 900000 1000000>;
|
opp-microvolt-L2 = <875000 875000 1000000>;
|
opp-microvolt-L3 = <875000 875000 1000000>;
|
};
|
opp-900000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = /bits/ 64 <900000000>;
|
opp-microvolt = <975000 975000 1000000>;
|
opp-microvolt-L0 = <975000 975000 1000000>;
|
opp-microvolt-L1 = <950000 950000 1000000>;
|
opp-microvolt-L2 = <925000 925000 1000000>;
|
opp-microvolt-L3 = <900000 900000 1000000>;
|
};
|
opp-1000000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = /bits/ 64 <1000000000>;
|
opp-microvolt = <1000000 1000000 1000000>;
|
opp-microvolt-L0 = <1000000 1000000 1000000>;
|
opp-microvolt-L1 = <975000 975000 1000000>;
|
opp-microvolt-L2 = <950000 950000 1000000>;
|
opp-microvolt-L3 = <925000 925000 1000000>;
|
status = "disabled";
|
};
|
|
/* RK3568J npu OPPs */
|
opp-j-600000000 {
|
opp-supported-hw = <0x04 0xffff>;
|
opp-hz = /bits/ 64 <600000000>;
|
opp-microvolt = <900000 900000 1000000>;
|
};
|
|
/* RK3568M npu OPPs */
|
opp-m-900000000 {
|
opp-supported-hw = <0x02 0xffff>;
|
opp-hz = /bits/ 64 <900000000>;
|
opp-microvolt = <925000 925000 1000000>;
|
};
|
};
|
|
bus_npu: bus-npu {
|
compatible = "rockchip,rk3568-bus";
|
rockchip,busfreq-policy = "clkfreq";
|
clocks = <&scmi_clk 2>;
|
clock-names = "bus";
|
operating-points-v2 = <&bus_npu_opp_table>;
|
status = "disabled";
|
};
|
|
bus_npu_opp_table: bus-npu-opp-table {
|
compatible = "operating-points-v2";
|
opp-shared;
|
|
nvmem-cells = <&core_pvtm>;
|
nvmem-cell-names = "pvtm";
|
rockchip,pvtm-voltage-sel = <
|
0 84000 0
|
84001 91000 1
|
91001 100000 2
|
>;
|
rockchip,pvtm-ch = <0 5>;
|
|
opp-700000000 {
|
opp-hz = /bits/ 64 <700000000>;
|
opp-microvolt = <900000>;
|
opp-microvolt-L0 = <900000>;
|
opp-microvolt-L1 = <875000>;
|
opp-microvolt-L2 = <875000>;
|
};
|
opp-900000000 {
|
opp-hz = /bits/ 64 <900000000>;
|
opp-microvolt = <900000>;
|
};
|
opp-1000000000 {
|
opp-hz = /bits/ 64 <1000000000>;
|
opp-microvolt = <950000>;
|
opp-microvolt-L0 = <950000>;
|
opp-microvolt-L1 = <925000>;
|
opp-microvolt-L2 = <900000>;
|
};
|
};
|
|
rknpu_mmu: iommu@fde4b000 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfde4b000 0x0 0x40>;
|
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "rknpu_mmu";
|
clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>;
|
clock-names = "aclk", "iface";
|
power-domains = <&power RK3568_PD_NPU>;
|
#iommu-cells = <0>;
|
status = "disabled";
|
};
|
|
gpu: gpu@fde60000 {
|
compatible = "arm,mali-bifrost";
|
reg = <0x0 0xfde60000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "GPU", "MMU", "JOB";
|
|
upthreshold = <40>;
|
downdifferential = <10>;
|
|
clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
|
clock-names = "clk_mali", "clk_gpu";
|
power-domains = <&power RK3568_PD_GPU>;
|
#cooling-cells = <2>;
|
operating-points-v2 = <&gpu_opp_table>;
|
|
status = "disabled";
|
gpu_power_model: power-model {
|
compatible = "simple-power-model";
|
leakage-range= <5 15>;
|
ls = <(-24002) 22823 0>;
|
static-coefficient = <100000>;
|
dynamic-coefficient = <953>;
|
ts = <(-108890) 63610 (-1355) 20>;
|
thermal-zone = "gpu-thermal";
|
};
|
};
|
|
gpu_opp_table: opp-table2 {
|
compatible = "operating-points-v2";
|
|
mbist-vmin = <825000 900000 950000>;
|
nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>,
|
<&specification_serial_number>, <&remark_spec_serial_number>;
|
nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
|
"specification_serial_number", "remark_spec_serial_number";
|
rockchip,supported-hw;
|
rockchip,max-volt = <1000000>;
|
rockchip,temp-hysteresis = <5000>;
|
rockchip,low-temp = <0>;
|
rockchip,low-temp-adjust-volt = <
|
/* MHz MHz uV */
|
0 800 50000
|
>;
|
rockchip,pvtm-voltage-sel = <
|
0 84000 0
|
84001 87000 1
|
87001 91000 2
|
91001 100000 3
|
>;
|
rockchip,pvtm-ch = <0 5>;
|
|
/* RK3568 && RK3568M gpu OPPs */
|
opp-200000000 {
|
opp-supported-hw = <0xfb 0xffff>;
|
opp-hz = /bits/ 64 <200000000>;
|
opp-microvolt = <850000 850000 1000000>;
|
};
|
opp-300000000 {
|
opp-supported-hw = <0xfb 0xffff>;
|
opp-hz = /bits/ 64 <300000000>;
|
opp-microvolt = <850000 850000 1000000>;
|
};
|
opp-400000000 {
|
opp-supported-hw = <0xfb 0xffff>;
|
opp-hz = /bits/ 64 <400000000>;
|
opp-microvolt = <850000 850000 1000000>;
|
};
|
opp-600000000 {
|
opp-supported-hw = <0xfb 0xffff>;
|
opp-hz = /bits/ 64 <600000000>;
|
opp-microvolt = <900000 900000 1000000>;
|
opp-microvolt-L0 = <900000 900000 1000000>;
|
opp-microvolt-L1 = <875000 875000 1000000>;
|
opp-microvolt-L2 = <850000 850000 1000000>;
|
opp-microvolt-L3 = <850000 850000 1000000>;
|
};
|
opp-700000000 {
|
opp-supported-hw = <0xfb 0xffff>;
|
opp-hz = /bits/ 64 <700000000>;
|
opp-microvolt = <950000 950000 1000000>;
|
opp-microvolt-L0 = <950000 950000 1000000>;
|
opp-microvolt-L1 = <925000 925000 1000000>;
|
opp-microvolt-L2 = <900000 900000 1000000>;
|
opp-microvolt-L3 = <875000 875000 1000000>;
|
};
|
opp-800000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = /bits/ 64 <800000000>;
|
opp-microvolt = <1000000 1000000 1000000>;
|
opp-microvolt-L0 = <1000000 1000000 1000000>;
|
opp-microvolt-L1 = <975000 975000 1000000>;
|
opp-microvolt-L2 = <950000 950000 1000000>;
|
opp-microvolt-L3 = <925000 925000 1000000>;
|
};
|
|
/* RK3568J gpu OPPs */
|
opp-j-600000000 {
|
opp-supported-hw = <0x04 0xffff>;
|
opp-hz = /bits/ 64 <600000000>;
|
opp-microvolt = <900000 900000 1000000>;
|
};
|
|
/* RK3568M gpu OPPs */
|
opp-m-800000000 {
|
opp-supported-hw = <0x02 0xffff>;
|
opp-hz = /bits/ 64 <800000000>;
|
opp-microvolt = <950000 950000 1000000>;
|
};
|
|
};
|
|
pvtm@fde80000 {
|
compatible = "rockchip,rk3568-gpu-pvtm";
|
reg = <0x0 0xfde80000 0x0 0x100>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
pvtm@1 {
|
reg = <1>;
|
clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>;
|
clock-names = "clk", "pclk";
|
resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>;
|
reset-names = "rts", "rst-p";
|
thermal-zone = "gpu-thermal";
|
};
|
};
|
|
pvtm@fde90000 {
|
compatible = "rockchip,rk3568-npu-pvtm";
|
reg = <0x0 0xfde90000 0x0 0x100>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
pvtm@2 {
|
reg = <2>;
|
clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>,
|
<&cru HCLK_NPU_PRE>;
|
clock-names = "clk", "pclk", "hclk";
|
resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>;
|
reset-names = "rts", "rst-p";
|
thermal-zone = "soc-thermal";
|
};
|
};
|
|
vdpu: vdpu@fdea0400 {
|
compatible = "rockchip,vpu-decoder-v2";
|
reg = <0x0 0xfdea0400 0x0 0x400>;
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "irq_dec";
|
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
|
reset-names = "video_a", "video_h";
|
iommus = <&vdpu_mmu>;
|
power-domains = <&power RK3568_PD_VPU>;
|
rockchip,srv = <&mpp_srv>;
|
rockchip,taskqueue-node = <0>;
|
rockchip,resetgroup-node = <0>;
|
status = "disabled";
|
};
|
|
vdpu_mmu: iommu@fdea0800 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdea0800 0x0 0x40>;
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "vdpu_mmu";
|
clock-names = "aclk", "iface";
|
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
power-domains = <&power RK3568_PD_VPU>;
|
#iommu-cells = <0>;
|
status = "disabled";
|
};
|
|
rk_rga: rk_rga@fdeb0000 {
|
compatible = "rockchip,rga2";
|
reg = <0x0 0xfdeb0000 0x0 0x1000>;
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
|
clock-names = "aclk_rga", "hclk_rga", "clk_rga";
|
power-domains = <&power RK3568_PD_RGA>;
|
status = "disabled";
|
};
|
|
ebc: ebc@fdec0000 {
|
compatible = "rockchip,rk3568-ebc-tcon";
|
reg = <0x0 0xfdec0000 0x0 0x5000>;
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>;
|
clock-names = "hclk", "dclk";
|
power-domains = <&power RK3568_PD_RGA>;
|
rockchip,grf = <&grf>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&ebc_pins>;
|
status = "disabled";
|
};
|
|
jpegd: jpegd@fded0000 {
|
compatible = "rockchip,rkv-jpeg-decoder-v1";
|
reg = <0x0 0xfded0000 0x0 0x400>;
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
rockchip,disable-auto-freq;
|
resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>;
|
reset-names = "video_a", "video_h";
|
iommus = <&jpegd_mmu>;
|
rockchip,srv = <&mpp_srv>;
|
rockchip,taskqueue-node = <1>;
|
rockchip,resetgroup-node = <1>;
|
power-domains = <&power RK3568_PD_RGA>;
|
status = "disabled";
|
};
|
|
jpegd_mmu: iommu@fded0480 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfded0480 0x0 0x40>;
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "jpegd_mmu";
|
clock-names = "aclk", "iface";
|
clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
|
power-domains = <&power RK3568_PD_RGA>;
|
#iommu-cells = <0>;
|
status = "disabled";
|
};
|
|
vepu: vepu@fdee0000 {
|
compatible = "rockchip,vpu-encoder-v2";
|
reg = <0x0 0xfdee0000 0x0 0x400>;
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
rockchip,disable-auto-freq;
|
resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>;
|
reset-names = "video_a", "video_h";
|
iommus = <&vepu_mmu>;
|
rockchip,srv = <&mpp_srv>;
|
rockchip,taskqueue-node = <2>;
|
rockchip,resetgroup-node = <2>;
|
power-domains = <&power RK3568_PD_RGA>;
|
status = "disabled";
|
};
|
|
vepu_mmu: iommu@fdee0800 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdee0800 0x0 0x40>;
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "vepu_mmu";
|
clock-names = "aclk", "iface";
|
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
|
power-domains = <&power RK3568_PD_RGA>;
|
#iommu-cells = <0>;
|
status = "disabled";
|
};
|
|
iep: iep@fdef0000 {
|
compatible = "rockchip,iep-v2";
|
reg = <0x0 0xfdef0000 0x0 0x500>;
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>;
|
clock-names = "aclk", "hclk", "sclk";
|
resets = <&cru SRST_A_IEP>, <&cru SRST_H_IEP>,
|
<&cru SRST_IEP_CORE>;
|
reset-names = "rst_a", "rst_h", "rst_s";
|
power-domains = <&power RK3568_PD_RGA>;
|
rockchip,srv = <&mpp_srv>;
|
rockchip,taskqueue-node = <5>;
|
rockchip,resetgroup-node = <5>;
|
iommus = <&iep_mmu>;
|
status = "disabled";
|
};
|
|
iep_mmu: iommu@fdef0800 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdef0800 0x0 0x100>;
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "iep_mmu";
|
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
|
clock-names = "aclk", "iface";
|
#iommu-cells = <0>;
|
power-domains = <&power RK3568_PD_RGA>;
|
//rockchip,disable-device-link-resume;
|
status = "disabled";
|
};
|
|
eink: eink@fdf00000 {
|
compatible = "rockchip,rk3568-eink-tcon";
|
reg = <0x0 0xfdf00000 0x0 0x74>;
|
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>;
|
clock-names = "pclk", "hclk";
|
status = "disabled";
|
};
|
|
rkvenc: rkvenc@fdf40000 {
|
compatible = "rockchip,rkv-encoder-v1";
|
reg = <0x0 0xfdf40000 0x0 0x400>;
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "irq_enc";
|
clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>,
|
<&cru CLK_RKVENC_CORE>;
|
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
|
rockchip,normal-rates = <297000000>, <0>, <297000000>;
|
resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>,
|
<&cru SRST_RKVENC_CORE>;
|
reset-names = "video_a", "video_h", "video_core";
|
assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
|
assigned-clock-rates = <297000000>, <297000000>;
|
iommus = <&rkvenc_mmu>;
|
node-name = "rkvenc";
|
rockchip,srv = <&mpp_srv>;
|
rockchip,taskqueue-node = <3>;
|
rockchip,resetgroup-node = <3>;
|
power-domains = <&power RK3568_PD_RKVENC>;
|
operating-points-v2 = <&rkvenc_opp_table>;
|
status = "disabled";
|
};
|
|
rkvenc_opp_table: rkvenc-opp-table {
|
compatible = "operating-points-v2";
|
|
nvmem-cells = <&core_pvtm>;
|
nvmem-cell-names = "pvtm";
|
rockchip,pvtm-voltage-sel = <
|
0 84000 0
|
84001 91000 1
|
91001 100000 2
|
>;
|
rockchip,pvtm-ch = <0 5>;
|
|
opp-297000000 {
|
opp-hz = /bits/ 64 <297000000>;
|
opp-microvolt = <900000>;
|
opp-microvolt-L0 = <900000>;
|
opp-microvolt-L1 = <875000>;
|
opp-microvolt-L2 = <875000>;
|
};
|
opp-400000000 {
|
opp-hz = /bits/ 64 <400000000>;
|
opp-microvolt = <950000>;
|
opp-microvolt-L0 = <950000>;
|
opp-microvolt-L1 = <925000>;
|
opp-microvolt-L2 = <900000>;
|
};
|
};
|
|
rkvenc_mmu: iommu@fdf40f00 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>;
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
|
clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
|
clock-names = "aclk", "iface";
|
rockchip,disable-mmu-reset;
|
rockchip,enable-cmd-retry;
|
#iommu-cells = <0>;
|
power-domains = <&power RK3568_PD_RKVENC>;
|
status = "disabled";
|
};
|
|
rkvdec: rkvdec@fdf80200 {
|
compatible = "rockchip,rkv-decoder-rk3568", "rockchip,rkv-decoder-v2";
|
reg = <0x0 0xfdf80200 0x0 0x400>, <0x0 0xfdf80100 0x0 0x100>;
|
reg-names = "regs", "link";
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "irq_dec";
|
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
|
<&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>,
|
<&cru CLK_RKVDEC_HEVC_CA>;
|
clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac",
|
"clk_core", "clk_hevc_cabac";
|
rockchip,normal-rates = <297000000>, <0>, <297000000>,
|
<297000000>, <600000000>;
|
rockchip,advanced-rates = <396000000>, <0>, <396000000>,
|
<396000000>, <600000000>;
|
rockchip,default-max-load = <2088960>;
|
resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>,
|
<&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>,
|
<&cru SRST_RKVDEC_HEVC_CA>;
|
assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>,
|
<&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>;
|
assigned-clock-rates = <297000000>, <297000000>, <297000000>, <297000000>;
|
reset-names = "video_a", "video_h", "video_cabac",
|
"video_core", "video_hevc_cabac";
|
power-domains = <&power RK3568_PD_RKVDEC>;
|
operating-points-v2 = <&rkvdec_opp_table>;
|
vdec-supply = <&vdd_logic>;
|
iommus = <&rkvdec_mmu>;
|
rockchip,srv = <&mpp_srv>;
|
rockchip,taskqueue-node = <4>;
|
rockchip,resetgroup-node = <4>;
|
rockchip,sram = <&rkvdec_sram>;
|
/* rcb_iova: start and size */
|
rockchip,rcb-iova = <0x10000000 65536>;
|
rockchip,rcb-min-width = <512>;
|
rockchip,task-capacity = <16>;
|
status = "disabled";
|
};
|
|
rkvdec_opp_table: rkvdec-opp-table {
|
compatible = "operating-points-v2";
|
|
nvmem-cells = <&log_leakage>, <&core_pvtm>;
|
nvmem-cell-names = "leakage", "pvtm";
|
rockchip,leakage-voltage-sel = <
|
1 80 0
|
81 254 1
|
>;
|
rockchip,pvtm-voltage-sel = <
|
0 84000 0
|
84001 100000 1
|
>;
|
rockchip,pvtm-ch = <0 5>;
|
|
opp-297000000 {
|
opp-hz = /bits/ 64 <297000000>;
|
opp-microvolt = <900000>;
|
opp-microvolt-L0 = <900000>;
|
opp-microvolt-L1 = <875000>;
|
};
|
opp-400000000 {
|
opp-hz = /bits/ 64 <400000000>;
|
opp-microvolt = <900000>;
|
};
|
};
|
|
rkvdec_mmu: iommu@fdf80800 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>;
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "rkvdec_mmu";
|
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
|
clock-names = "aclk", "iface";
|
power-domains = <&power RK3568_PD_RKVDEC>;
|
#iommu-cells = <0>;
|
status = "disabled";
|
};
|
|
mipi_csi2_hw: mipi-csi2-hw@fdfb0000 {
|
compatible = "rockchip,rk3568-mipi-csi2-hw";
|
reg = <0x0 0xfdfb0000 0x0 0x10000>;
|
reg-names = "csihost_regs";
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "csi-intr1", "csi-intr2";
|
clocks = <&cru PCLK_CSI2HOST1>;
|
clock-names = "pclk_csi2host";
|
resets = <&cru SRST_P_CSI2HOST1>;
|
reset-names = "srst_csihost_p";
|
status = "disabled";
|
};
|
|
rkcif: rkcif@fdfe0000 {
|
compatible = "rockchip,rk3568-cif";
|
reg = <0x0 0xfdfe0000 0x0 0x8000>;
|
reg-names = "cif_regs";
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "cif-intr";
|
|
clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
|
<&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>;
|
clock-names = "aclk_cif", "hclk_cif",
|
"dclk_cif", "iclk_cif_g";
|
resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
|
<&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
|
<&cru SRST_I_VICAP>;
|
reset-names = "rst_cif_a", "rst_cif_h",
|
"rst_cif_d", "rst_cif_p",
|
"rst_cif_i";
|
assigned-clocks = <&cru DCLK_VICAP>;
|
assigned-clock-rates = <300000000>;
|
power-domains = <&power RK3568_PD_VI>;
|
rockchip,grf = <&grf>;
|
iommus = <&rkcif_mmu>;
|
status = "disabled";
|
};
|
|
rkcif_mmu: iommu@fdfe0800 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdfe0800 0x0 0x100>;
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "cif_mmu";
|
clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
|
clock-names = "aclk", "iface";
|
power-domains = <&power RK3568_PD_VI>;
|
rockchip,disable-mmu-reset;
|
#iommu-cells = <0>;
|
status = "disabled";
|
};
|
|
rkcif_dvp: rkcif_dvp {
|
compatible = "rockchip,rkcif-dvp";
|
rockchip,hw = <&rkcif>;
|
status = "disabled";
|
};
|
|
rkcif_dvp_sditf: rkcif_dvp_sditf {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <&rkcif_dvp>;
|
status = "disabled";
|
};
|
|
rkcif_mipi_lvds: rkcif_mipi_lvds {
|
compatible = "rockchip,rkcif-mipi-lvds";
|
rockchip,hw = <&rkcif>;
|
status = "disabled";
|
};
|
|
rkcif_mipi_lvds_sditf: rkcif_mipi_lvds_sditf {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <&rkcif_mipi_lvds>;
|
status = "disabled";
|
};
|
|
rkisp: rkisp@fdff0000 {
|
compatible = "rockchip,rk3568-rkisp";
|
reg = <0x0 0xfdff0000 0x0 0x10000>;
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
|
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>;
|
clock-names = "aclk_isp", "hclk_isp", "clk_isp";
|
resets = <&cru SRST_ISP>, <&cru SRST_H_ISP>;
|
reset-names = "isp", "isp-h";
|
rockchip,grf = <&grf>;
|
power-domains = <&power RK3568_PD_VI>;
|
iommus = <&rkisp_mmu>;
|
rockchip,iq-feature = /bits/ 64 <0x1BFBFFFE67FF>;
|
status = "disabled";
|
};
|
|
rkisp_mmu: iommu@fdff1a00 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdff1a00 0x0 0x100>;
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "isp_mmu";
|
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
|
clock-names = "aclk", "iface";
|
power-domains = <&power RK3568_PD_VI>;
|
#iommu-cells = <0>;
|
rockchip,disable-mmu-reset;
|
status = "disabled";
|
};
|
|
rkisp_vir0: rkisp-vir0 {
|
compatible = "rockchip,rkisp-vir";
|
rockchip,hw = <&rkisp>;
|
status = "disabled";
|
};
|
|
rkisp_vir1: rkisp-vir1 {
|
compatible = "rockchip,rkisp-vir";
|
rockchip,hw = <&rkisp>;
|
status = "disabled";
|
};
|
|
gmac_uio1: uio@fe010000 {
|
compatible = "rockchip,uio-gmac";
|
reg = <0x0 0xfe010000 0x0 0x10000>;
|
rockchip,ethernet = <&gmac1>;
|
status = "disabled";
|
};
|
|
gmac1: ethernet@fe010000 {
|
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
reg = <0x0 0xfe010000 0x0 0x10000>;
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "macirq", "eth_wake_irq";
|
rockchip,grf = <&grf>;
|
clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
|
<&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
|
<&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
|
<&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
|
<&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
|
clock-names = "stmmaceth", "mac_clk_rx",
|
"mac_clk_tx", "clk_mac_refout",
|
"aclk_mac", "pclk_mac",
|
"clk_mac_speed", "ptp_ref",
|
"pclk_xpcs", "clk_xpcs_eee";
|
resets = <&cru SRST_A_GMAC1>;
|
reset-names = "stmmaceth";
|
|
snps,mixed-burst;
|
snps,tso;
|
|
snps,axi-config = <&gmac1_stmmac_axi_setup>;
|
snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
|
snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
|
status = "disabled";
|
|
mdio1: mdio {
|
compatible = "snps,dwmac-mdio";
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
};
|
|
gmac1_stmmac_axi_setup: stmmac-axi-config {
|
snps,wr_osr_lmt = <4>;
|
snps,rd_osr_lmt = <8>;
|
snps,blen = <0 0 0 0 16 8 4>;
|
};
|
|
gmac1_mtl_rx_setup: rx-queues-config {
|
snps,rx-queues-to-use = <1>;
|
queue0 {};
|
};
|
|
gmac1_mtl_tx_setup: tx-queues-config {
|
snps,tx-queues-to-use = <1>;
|
queue0 {};
|
};
|
};
|
|
vop: vop@fe040000 {
|
compatible = "rockchip,rk3568-vop";
|
reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
|
reg-names = "regs", "gamma_lut";
|
rockchip,grf = <&grf>;
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
|
clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
|
iommus = <&vop_mmu>;
|
power-domains = <&power RK3568_PD_VO>;
|
status = "disabled";
|
|
vop_out: ports {
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
vp0: port@0 {
|
#address-cells = <1>;
|
#size-cells = <0>;
|
reg = <0>;
|
|
vp0_out_dsi0: endpoint@0 {
|
reg = <0>;
|
remote-endpoint = <&dsi0_in_vp0>;
|
};
|
|
vp0_out_dsi1: endpoint@1 {
|
reg = <1>;
|
remote-endpoint = <&dsi1_in_vp0>;
|
};
|
|
vp0_out_edp: endpoint@2 {
|
reg = <2>;
|
remote-endpoint = <&edp_in_vp0>;
|
};
|
|
vp0_out_hdmi: endpoint@3 {
|
reg = <3>;
|
remote-endpoint = <&hdmi_in_vp0>;
|
};
|
};
|
|
vp1: port@1 {
|
#address-cells = <1>;
|
#size-cells = <0>;
|
reg = <1>;
|
|
vp1_out_dsi0: endpoint@0 {
|
reg = <0>;
|
remote-endpoint = <&dsi0_in_vp1>;
|
};
|
|
vp1_out_dsi1: endpoint@1 {
|
reg = <1>;
|
remote-endpoint = <&dsi1_in_vp1>;
|
};
|
|
vp1_out_edp: endpoint@2 {
|
reg = <2>;
|
remote-endpoint = <&edp_in_vp1>;
|
};
|
|
vp1_out_hdmi: endpoint@3 {
|
reg = <3>;
|
remote-endpoint = <&hdmi_in_vp1>;
|
};
|
|
vp1_out_lvds: endpoint@4 {
|
reg = <4>;
|
remote-endpoint = <&lvds_in_vp1>;
|
};
|
|
vp1_out_lvds1: endpoint@5 {
|
reg = <5>;
|
remote-endpoint = <&lvds1_in_vp1>;
|
};
|
};
|
|
vp2: port@2 {
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
reg = <2>;
|
|
vp2_out_lvds: endpoint@0 {
|
reg = <0>;
|
remote-endpoint = <&lvds_in_vp2>;
|
};
|
|
vp2_out_rgb: endpoint@1 {
|
reg = <1>;
|
remote-endpoint = <&rgb_in_vp2>;
|
};
|
|
vp2_out_lvds1: endpoint@2 {
|
reg = <2>;
|
remote-endpoint = <&lvds1_in_vp2>;
|
};
|
};
|
};
|
};
|
|
vop_mmu: iommu@fe043e00 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "vop_mmu";
|
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
clock-names = "aclk", "iface";
|
#iommu-cells = <0>;
|
rockchip,disable-device-link-resume;
|
status = "disabled";
|
};
|
|
dsi0: dsi@fe060000 {
|
compatible = "rockchip,rk3568-mipi-dsi";
|
reg = <0x0 0xfe060000 0x0 0x10000>;
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
|
clock-names = "pclk", "hclk";
|
resets = <&cru SRST_P_DSITX_0>;
|
reset-names = "apb";
|
phys = <&video_phy0>;
|
phy-names = "dphy";
|
power-domains = <&power RK3568_PD_VO>;
|
rockchip,grf = <&grf>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
status = "disabled";
|
|
ports {
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
dsi0_in: port@0 {
|
reg = <0>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
dsi0_in_vp0: endpoint@0 {
|
reg = <0>;
|
remote-endpoint = <&vp0_out_dsi0>;
|
status = "disabled";
|
};
|
|
dsi0_in_vp1: endpoint@1 {
|
reg = <1>;
|
remote-endpoint = <&vp1_out_dsi0>;
|
status = "disabled";
|
};
|
};
|
};
|
};
|
|
dsi1: dsi@fe070000 {
|
compatible = "rockchip,rk3568-mipi-dsi";
|
reg = <0x0 0xfe070000 0x0 0x10000>;
|
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
|
clock-names = "pclk", "hclk";
|
resets = <&cru SRST_P_DSITX_1>;
|
reset-names = "apb";
|
phys = <&video_phy1>;
|
phy-names = "dphy";
|
power-domains = <&power RK3568_PD_VO>;
|
rockchip,grf = <&grf>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
status = "disabled";
|
|
ports {
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
dsi1_in: port@0 {
|
reg = <0>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
dsi1_in_vp0: endpoint@0 {
|
reg = <0>;
|
remote-endpoint = <&vp0_out_dsi1>;
|
status = "disabled";
|
};
|
|
dsi1_in_vp1: endpoint@1 {
|
reg = <1>;
|
remote-endpoint = <&vp1_out_dsi1>;
|
status = "disabled";
|
};
|
};
|
};
|
};
|
|
hdmi: hdmi@fe0a0000 {
|
compatible = "rockchip,rk3568-dw-hdmi";
|
reg = <0x0 0xfe0a0000 0x0 0x20000>;
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru PCLK_HDMI_HOST>,
|
<&cru CLK_HDMI_SFR>,
|
<&cru CLK_HDMI_CEC>,
|
<&pmucru PLL_HPLL>,
|
<&cru HCLK_VOP>;
|
clock-names = "iahb", "isfr", "cec", "ref", "hclk";
|
power-domains = <&power RK3568_PD_VO>;
|
reg-io-width = <4>;
|
rockchip,grf = <&grf>;
|
#sound-dai-cells = <0>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
|
status = "disabled";
|
|
ports {
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
port@0 {
|
reg = <0>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
hdmi_in_vp0: endpoint@0 {
|
reg = <0>;
|
remote-endpoint = <&vp0_out_hdmi>;
|
status = "disabled";
|
};
|
|
hdmi_in_vp1: endpoint@1 {
|
reg = <1>;
|
remote-endpoint = <&vp1_out_hdmi>;
|
status = "disabled";
|
};
|
};
|
};
|
};
|
|
edp: edp@fe0c0000 {
|
compatible = "rockchip,rk3568-edp";
|
reg = <0x0 0xfe0c0000 0x0 0x10000>;
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>,
|
<&cru CLK_EDP_200M>, <&cru HCLK_VO>;
|
clock-names = "dp", "pclk", "spdif", "hclk";
|
resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>;
|
reset-names = "dp", "apb";
|
phys = <&edp_phy>;
|
phy-names = "dp";
|
power-domains = <&power RK3568_PD_VO>;
|
status = "disabled";
|
|
ports {
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
edp_in: port@0 {
|
reg = <0>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
|
edp_in_vp0: endpoint@0 {
|
reg = <0>;
|
remote-endpoint = <&vp0_out_edp>;
|
status = "disabled";
|
};
|
|
edp_in_vp1: endpoint@1 {
|
reg = <1>;
|
remote-endpoint = <&vp1_out_edp>;
|
status = "disabled";
|
};
|
};
|
};
|
};
|
|
nocp_cpu: nocp-cpu@fe102000 {
|
compatible = "rockchip,rk3568-nocp";
|
reg = <0x0 0xfe102000 0x0 0x400>;
|
};
|
|
nocp_gpu_vpu_rga_venc: nocp-gpu-vpu-rga-venc@fe102400 {
|
compatible = "rockchip,rk3568-nocp";
|
reg = <0x0 0xfe102400 0x0 0x400>;
|
};
|
|
nocp_npu_vdec: nocp-vdec@fe102800 {
|
compatible = "rockchip,rk3568-nocp";
|
reg = <0x0 0xfe102800 0x0 0x400>;
|
};
|
|
nocp_vi_usb_peri_pipe: nocp-vi-usb-peri-pipe@fe102c00 {
|
compatible = "rockchip,rk3568-nocp";
|
reg = <0x0 0xfe102c00 0x0 0x400>;
|
};
|
|
nocp_vo: nocp-vo@fe103000 {
|
compatible = "rockchip,rk3568-nocp";
|
reg = <0x0 0xfe103000 0x0 0x400>;
|
};
|
|
qos_gpu: qos@fe128000 {
|
compatible = "syscon";
|
reg = <0x0 0xfe128000 0x0 0x20>;
|
};
|
|
qos_rkvenc_rd_m0: qos@fe138080 {
|
compatible = "syscon";
|
reg = <0x0 0xfe138080 0x0 0x20>;
|
};
|
|
qos_rkvenc_rd_m1: qos@fe138100 {
|
compatible = "syscon";
|
reg = <0x0 0xfe138100 0x0 0x20>;
|
};
|
|
qos_rkvenc_wr_m0: qos@fe138180 {
|
compatible = "syscon";
|
reg = <0x0 0xfe138180 0x0 0x20>;
|
};
|
|
qos_isp: qos@fe148000 {
|
compatible = "syscon";
|
reg = <0x0 0xfe148000 0x0 0x20>;
|
};
|
|
qos_vicap0: qos@fe148080 {
|
compatible = "syscon";
|
reg = <0x0 0xfe148080 0x0 0x20>;
|
};
|
|
qos_vicap1: qos@fe148100 {
|
compatible = "syscon";
|
reg = <0x0 0xfe148100 0x0 0x20>;
|
};
|
|
qos_vpu: qos@fe150000 {
|
compatible = "syscon";
|
reg = <0x0 0xfe150000 0x0 0x20>;
|
};
|
|
qos_ebc: qos@fe158000 {
|
compatible = "syscon";
|
reg = <0x0 0xfe158000 0x0 0x20>;
|
};
|
|
qos_iep: qos@fe158100 {
|
compatible = "syscon";
|
reg = <0x0 0xfe158100 0x0 0x20>;
|
};
|
|
qos_jpeg_dec: qos@fe158180 {
|
compatible = "syscon";
|
reg = <0x0 0xfe158180 0x0 0x20>;
|
};
|
|
qos_jpeg_enc: qos@fe158200 {
|
compatible = "syscon";
|
reg = <0x0 0xfe158200 0x0 0x20>;
|
};
|
|
qos_rga_rd: qos@fe158280 {
|
compatible = "syscon";
|
reg = <0x0 0xfe158280 0x0 0x20>;
|
};
|
|
qos_rga_wr: qos@fe158300 {
|
compatible = "syscon";
|
reg = <0x0 0xfe158300 0x0 0x20>;
|
};
|
|
qos_npu: qos@fe180000 {
|
compatible = "syscon";
|
reg = <0x0 0xfe180000 0x0 0x20>;
|
};
|
|
qos_pcie2x1: qos@fe190000 {
|
compatible = "syscon";
|
reg = <0x0 0xfe190000 0x0 0x20>;
|
};
|
|
qos_pcie3x1: qos@fe190080 {
|
compatible = "syscon";
|
reg = <0x0 0xfe190080 0x0 0x20>;
|
};
|
|
qos_pcie3x2: qos@fe190100 {
|
compatible = "syscon";
|
reg = <0x0 0xfe190100 0x0 0x20>;
|
};
|
|
qos_sata0: qos@fe190200 {
|
compatible = "syscon";
|
reg = <0x0 0xfe190200 0x0 0x20>;
|
};
|
|
qos_sata1: qos@fe190280 {
|
compatible = "syscon";
|
reg = <0x0 0xfe190280 0x0 0x20>;
|
};
|
|
qos_sata2: qos@fe190300 {
|
compatible = "syscon";
|
reg = <0x0 0xfe190300 0x0 0x20>;
|
};
|
|
qos_usb3_0: qos@fe190380 {
|
compatible = "syscon";
|
reg = <0x0 0xfe190380 0x0 0x20>;
|
};
|
|
qos_usb3_1: qos@fe190400 {
|
compatible = "syscon";
|
reg = <0x0 0xfe190400 0x0 0x20>;
|
};
|
|
qos_rkvdec: qos@fe198000 {
|
compatible = "syscon";
|
reg = <0x0 0xfe198000 0x0 0x20>;
|
};
|
|
qos_hdcp: qos@fe1a8000 {
|
compatible = "syscon";
|
reg = <0x0 0xfe1a8000 0x0 0x20>;
|
};
|
|
qos_vop_m0: qos@fe1a8080 {
|
compatible = "syscon";
|
reg = <0x0 0xfe1a8080 0x0 0x20>;
|
};
|
|
qos_vop_m1: qos@fe1a8100 {
|
compatible = "syscon";
|
reg = <0x0 0xfe1a8100 0x0 0x20>;
|
};
|
|
sdmmc2: dwmmc@fe000000 {
|
compatible = "rockchip,rk3568-dw-mshc",
|
"rockchip,rk3288-dw-mshc";
|
reg = <0x0 0xfe000000 0x0 0x4000>;
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
max-frequency = <150000000>;
|
clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
|
<&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
fifo-depth = <0x100>;
|
resets = <&cru SRST_SDMMC2>;
|
reset-names = "reset";
|
status = "disabled";
|
};
|
|
dfi: dfi@fe230000 {
|
reg = <0x00 0xfe230000 0x00 0x400>;
|
compatible = "rockchip,rk3568-dfi";
|
rockchip,pmugrf = <&pmugrf>;
|
status = "disabled";
|
};
|
|
dmc: dmc {
|
compatible = "rockchip,rk3568-dmc";
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "complete";
|
devfreq-events = <&dfi>, <&nocp_cpu>;
|
clocks = <&scmi_clk 3>;
|
clock-names = "dmc_clk";
|
operating-points-v2 = <&dmc_opp_table>;
|
vop-bw-dmc-freq = <
|
/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
|
0 286 324000
|
287 99999 528000
|
>;
|
vop-frame-bw-dmc-freq = <
|
/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
|
0 620 324000
|
621 99999 780000
|
>;
|
cpu-bw-dmc-freq = <
|
/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
|
0 350 324000
|
351 400 528000
|
401 99999 780000
|
>;
|
upthreshold = <40>;
|
downdifferential = <20>;
|
system-status-level = <
|
/*system status freq level*/
|
SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH
|
SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH
|
SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW
|
SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH
|
SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH
|
SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH
|
SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH
|
SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH
|
SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH
|
>;
|
auto-min-freq = <324000>;
|
auto-freq-en = <1>;
|
#cooling-cells = <2>;
|
status = "disabled";
|
};
|
|
dmc_fsp: dmc-fsp {
|
compatible = "rockchip,rk3568-dmc-fsp";
|
|
debug_print_level = <0>;
|
ddr3_params = <&ddr3_params>;
|
ddr4_params = <&ddr4_params>;
|
lpddr3_params = <&lpddr3_params>;
|
lpddr4_params = <&lpddr4_params>;
|
lpddr4x_params = <&lpddr4x_params>;
|
|
status = "okay";
|
};
|
|
dmc_opp_table: dmc-opp-table {
|
compatible = "operating-points-v2";
|
|
mbist-vmin = <825000 900000 950000>;
|
nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>,
|
<&specification_serial_number>, <&remark_spec_serial_number>;
|
nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
|
"specification_serial_number", "remark_spec_serial_number";
|
rockchip,supported-hw;
|
rockchip,max-volt = <1000000>;
|
rockchip,temp-hysteresis = <5000>;
|
rockchip,low-temp = <0>;
|
rockchip,low-temp-adjust-volt = <
|
/* MHz MHz uV */
|
0 1560 75000
|
>;
|
rockchip,leakage-voltage-sel = <
|
1 80 0
|
81 254 1
|
>;
|
rockchip,pvtm-voltage-sel = <
|
0 84000 0
|
84001 100000 1
|
>;
|
rockchip,pvtm-ch = <0 5>;
|
|
/* RK3568 dmc OPPs */
|
opp-1560000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = /bits/ 64 <1560000000>;
|
opp-microvolt = <900000 900000 1000000>;
|
opp-microvolt-L0 = <900000 900000 1000000>;
|
opp-microvolt-L1 = <875000 875000 1000000>;
|
};
|
|
/* RK3568J/M dmc OPPs */
|
opp-j-m-1560000000 {
|
opp-supported-hw = <0x06 0xffff>;
|
opp-hz = /bits/ 64 <1560000000>;
|
opp-microvolt = <875000 875000 1000000>;
|
};
|
};
|
|
pcie2x1: pcie@fe260000 {
|
compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
|
#address-cells = <3>;
|
#size-cells = <2>;
|
bus-range = <0x0 0xf>;
|
clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
|
<&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
|
<&cru CLK_PCIE20_AUX_NDFT>;
|
clock-names = "aclk_mst", "aclk_slv",
|
"aclk_dbi", "pclk", "aux";
|
device_type = "pci";
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
#interrupt-cells = <1>;
|
interrupt-map-mask = <0 0 0 7>;
|
interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
|
<0 0 0 2 &pcie2x1_intc 1>,
|
<0 0 0 3 &pcie2x1_intc 2>,
|
<0 0 0 4 &pcie2x1_intc 3>;
|
linux,pci-domain = <0>;
|
num-ib-windows = <6>;
|
num-viewport = <8>;
|
num-ob-windows = <2>;
|
max-link-speed = <2>;
|
msi-map = <0x0 &its 0x0 0x1000>;
|
num-lanes = <1>;
|
phys = <&combphy2_psq PHY_TYPE_PCIE>;
|
phy-names = "pcie-phy";
|
power-domains = <&power RK3568_PD_PIPE>;
|
ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000
|
0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
|
0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x1e00000
|
0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
|
reg = <0x3 0xc0000000 0x0 0x400000>,
|
<0x0 0xfe260000 0x0 0x10000>;
|
reg-names = "pcie-dbi", "pcie-apb";
|
resets = <&cru SRST_PCIE20_POWERUP>;
|
reset-names = "pipe";
|
status = "disabled";
|
|
pcie2x1_intc: legacy-interrupt-controller {
|
interrupt-controller;
|
#address-cells = <0>;
|
#interrupt-cells = <1>;
|
interrupt-parent = <&gic>;
|
interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
|
};
|
};
|
|
pcie3x1: pcie@fe270000 {
|
compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
|
#address-cells = <3>;
|
#size-cells = <2>;
|
bus-range = <0x10 0x1f>;
|
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
|
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
|
<&cru CLK_PCIE30X1_AUX_NDFT>;
|
clock-names = "aclk_mst", "aclk_slv",
|
"aclk_dbi", "pclk", "aux";
|
device_type = "pci";
|
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
#interrupt-cells = <1>;
|
interrupt-map-mask = <0 0 0 7>;
|
interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
|
<0 0 0 2 &pcie3x1_intc 1>,
|
<0 0 0 3 &pcie3x1_intc 2>,
|
<0 0 0 4 &pcie3x1_intc 3>;
|
linux,pci-domain = <1>;
|
num-ib-windows = <6>;
|
num-ob-windows = <2>;
|
num-viewport = <8>;
|
max-link-speed = <3>;
|
msi-map = <0x1000 &its 0x1000 0x1000>;
|
num-lanes = <1>;
|
phys = <&pcie30phy>;
|
phy-names = "pcie-phy";
|
power-domains = <&power RK3568_PD_PIPE>;
|
ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000
|
0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000
|
0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x1e00000
|
0xc3000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;
|
reg = <0x3 0xc0400000 0x0 0x400000>,
|
<0x0 0xfe270000 0x0 0x10000>;
|
reg-names = "pcie-dbi", "pcie-apb";
|
resets = <&cru SRST_PCIE30X1_POWERUP>;
|
reset-names = "pipe";
|
/* rockchip,bifurcation; lane1 when using 1+1 */
|
status = "disabled";
|
|
pcie3x1_intc: legacy-interrupt-controller {
|
interrupt-controller;
|
#address-cells = <0>;
|
#interrupt-cells = <1>;
|
interrupt-parent = <&gic>;
|
interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
|
};
|
};
|
|
pcie3x2: pcie@fe280000 {
|
compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
|
#address-cells = <3>;
|
#size-cells = <2>;
|
bus-range = <0x20 0x2f>;
|
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
|
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
|
<&cru CLK_PCIE30X2_AUX_NDFT>;
|
clock-names = "aclk_mst", "aclk_slv",
|
"aclk_dbi", "pclk", "aux";
|
device_type = "pci";
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
#interrupt-cells = <1>;
|
interrupt-map-mask = <0 0 0 7>;
|
interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
<0 0 0 2 &pcie3x2_intc 1>,
|
<0 0 0 3 &pcie3x2_intc 2>,
|
<0 0 0 4 &pcie3x2_intc 3>;
|
linux,pci-domain = <2>;
|
num-ib-windows = <6>;
|
num-viewport = <8>;
|
num-ob-windows = <2>;
|
max-link-speed = <3>;
|
msi-map = <0x2000 &its 0x2000 0x1000>;
|
num-lanes = <2>;
|
phys = <&pcie30phy>;
|
phy-names = "pcie-phy";
|
power-domains = <&power RK3568_PD_PIPE>;
|
ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000
|
0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000
|
0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x1e00000
|
0xc3000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;
|
reg = <0x3 0xc0800000 0x0 0x400000>,
|
<0x0 0xfe280000 0x0 0x10000>;
|
reg-names = "pcie-dbi", "pcie-apb";
|
resets = <&cru SRST_PCIE30X2_POWERUP>;
|
reset-names = "pipe";
|
/* rockchip,bifurcation; lane0 when using 1+1 */
|
status = "disabled";
|
|
pcie3x2_intc: legacy-interrupt-controller {
|
interrupt-controller;
|
#address-cells = <0>;
|
#interrupt-cells = <1>;
|
interrupt-parent = <&gic>;
|
interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
|
};
|
};
|
|
gmac_uio0: uio@fe2a0000 {
|
compatible = "rockchip,uio-gmac";
|
reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
rockchip,ethernet = <&gmac0>;
|
status = "disabled";
|
};
|
|
gmac0: ethernet@fe2a0000 {
|
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
interrupt-names = "macirq", "eth_wake_irq";
|
rockchip,grf = <&grf>;
|
clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
|
<&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
|
clock-names = "stmmaceth", "mac_clk_rx",
|
"mac_clk_tx", "clk_mac_refout",
|
"aclk_mac", "pclk_mac",
|
"clk_mac_speed", "ptp_ref",
|
"pclk_xpcs", "clk_xpcs_eee";
|
resets = <&cru SRST_A_GMAC0>;
|
reset-names = "stmmaceth";
|
|
snps,mixed-burst;
|
snps,tso;
|
|
snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
status = "disabled";
|
|
mdio0: mdio {
|
compatible = "snps,dwmac-mdio";
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
};
|
|
gmac0_stmmac_axi_setup: stmmac-axi-config {
|
snps,wr_osr_lmt = <4>;
|
snps,rd_osr_lmt = <8>;
|
snps,blen = <0 0 0 0 16 8 4>;
|
};
|
|
gmac0_mtl_rx_setup: rx-queues-config {
|
snps,rx-queues-to-use = <1>;
|
queue0 {};
|
};
|
|
gmac0_mtl_tx_setup: tx-queues-config {
|
snps,tx-queues-to-use = <1>;
|
queue0 {};
|
};
|
};
|
|
sdmmc0: dwmmc@fe2b0000 {
|
compatible = "rockchip,rk3568-dw-mshc",
|
"rockchip,rk3288-dw-mshc";
|
reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
max-frequency = <150000000>;
|
clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
|
<&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
fifo-depth = <0x100>;
|
resets = <&cru SRST_SDMMC0>;
|
reset-names = "reset";
|
status = "disabled";
|
};
|
|
sdmmc1: dwmmc@fe2c0000 {
|
compatible = "rockchip,rk3568-dw-mshc",
|
"rockchip,rk3288-dw-mshc";
|
reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
max-frequency = <150000000>;
|
clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
|
<&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
fifo-depth = <0x100>;
|
resets = <&cru SRST_SDMMC1>;
|
reset-names = "reset";
|
status = "disabled";
|
};
|
|
sfc: spi@fe300000 {
|
compatible = "rockchip,sfc";
|
reg = <0x0 0xfe300000 0x0 0x4000>;
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
clock-names = "clk_sfc", "hclk_sfc";
|
assigned-clocks = <&cru SCLK_SFC>;
|
assigned-clock-rates = <100000000>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
status = "disabled";
|
};
|
|
sdhci: sdhci@fe310000 {
|
compatible = "rockchip,rk3568-dwcmshc", "rockchip,dwcmshc-sdhci";
|
reg = <0x0 0xfe310000 0x0 0x10000>;
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
|
<&cru CCLK_EMMC>;
|
assigned-clock-rates = <200000000>, <24000000>, <200000000>;
|
clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
|
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
|
<&cru TCLK_EMMC>;
|
clock-names = "core", "bus", "axi", "block", "timer";
|
resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
|
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
|
<&cru SRST_T_EMMC>;
|
reset-names = "core", "bus", "axi", "block", "timer";
|
status = "disabled";
|
};
|
|
nandc0: nandc@fe330000 {
|
compatible = "rockchip,rk-nandc-v9";
|
reg = <0x0 0xfe330000 0x0 0x4000>;
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
nandc_id = <0>;
|
clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>;
|
clock-names = "clk_nandc", "hclk_nandc";
|
status = "disabled";
|
};
|
|
crypto: crypto@fe380000 {
|
compatible = "rockchip,rk3568-crypto";
|
reg = <0x0 0xfe380000 0x0 0x4000>;
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>,
|
<&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>;
|
clock-names = "aclk", "hclk", "sclk", "apb_pclk";
|
assigned-clocks = <&cru CLK_CRYPTO_NS_CORE>;
|
assigned-clock-rates = <200000000>;
|
resets = <&cru SRST_CRYPTO_NS_CORE>;
|
reset-names = "crypto-rst";
|
status = "disabled";
|
};
|
|
rng: rng@fe388000 {
|
compatible = "rockchip,cryptov2-rng";
|
reg = <0x0 0xfe388000 0x0 0x2000>;
|
clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
|
clock-names = "clk_trng", "hclk_trng";
|
resets = <&cru SRST_TRNG_NS>;
|
reset-names = "reset";
|
status = "disabled";
|
};
|
|
otp: otp@fe38c000 {
|
compatible = "rockchip,rk3568-otp";
|
reg = <0x0 0xfe38c000 0x0 0x4000>;
|
#address-cells = <1>;
|
#size-cells = <1>;
|
clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>,
|
<&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>;
|
clock-names = "usr", "sbpi", "apb", "phy";
|
resets = <&cru SRST_OTPPHY>;
|
reset-names = "otp_phy";
|
|
/* Data cells */
|
cpu_code: cpu-code@2 {
|
reg = <0x02 0x2>;
|
};
|
specification_serial_number: specification-serial-number@7 {
|
reg = <0x07 0x1>;
|
bits = <0 5>;
|
};
|
otp_cpu_version: cpu-version@8 {
|
reg = <0x08 0x1>;
|
bits = <3 3>;
|
};
|
mbist_vmin: mbist-vmin@9 {
|
reg = <0x09 0x1>;
|
bits = <0 4>;
|
};
|
otp_id: id@a {
|
reg = <0x0a 0x10>;
|
};
|
cpu_leakage: cpu-leakage@1a {
|
reg = <0x1a 0x1>;
|
};
|
log_leakage: log-leakage@1b {
|
reg = <0x1b 0x1>;
|
};
|
npu_leakage: npu-leakage@1c {
|
reg = <0x1c 0x1>;
|
};
|
gpu_leakage: gpu-leakage@1d {
|
reg = <0x1d 0x1>;
|
};
|
core_pvtm:core-pvtm@2a {
|
reg = <0x2a 0x2>;
|
};
|
cpu_tsadc_trim_l: cpu-tsadc-trim-l@2e {
|
reg = <0x2e 0x1>;
|
};
|
cpu_tsadc_trim_h: cpu-tsadc-trim-h@2f {
|
reg = <0x2f 0x1>;
|
bits = <0 4>;
|
};
|
gpu_tsadc_trim_l: npu-tsadc-trim-l@30 {
|
reg = <0x30 0x1>;
|
};
|
gpu_tsadc_trim_h: npu-tsadc-trim-h@31 {
|
reg = <0x31 0x1>;
|
bits = <0 4>;
|
};
|
tsadc_trim_base_frac: tsadc-trim-base-frac@31 {
|
reg = <0x31 0x1>;
|
bits = <4 4>;
|
};
|
tsadc_trim_base: tsadc-trim-base@32 {
|
reg = <0x32 0x1>;
|
};
|
cpu_opp_info: cpu-opp-info@36 {
|
reg = <0x36 0x6>;
|
};
|
gpu_opp_info: gpu-opp-info@3c {
|
reg = <0x3c 0x6>;
|
};
|
npu_opp_info: npu-opp-info@42 {
|
reg = <0x42 0x6>;
|
};
|
dmc_opp_info: dmc-opp-info@48 {
|
reg = <0x48 0x6>;
|
};
|
remark_spec_serial_number: remark-spec-serial-number@56 {
|
reg = <0x56 0x1>;
|
bits = <0 5>;
|
};
|
};
|
|
i2s0_8ch: i2s@fe400000 {
|
compatible = "rockchip,rk3568-i2s-tdm";
|
reg = <0x0 0xfe400000 0x0 0x1000>;
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
dmas = <&dmac1 0>;
|
dma-names = "tx";
|
resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
|
reset-names = "tx-m", "rx-m";
|
rockchip,cru = <&cru>;
|
rockchip,grf = <&grf>;
|
rockchip,playback-only;
|
#sound-dai-cells = <0>;
|
status = "disabled";
|
};
|
|
i2s1_8ch: i2s@fe410000 {
|
compatible = "rockchip,rk3568-i2s-tdm";
|
reg = <0x0 0xfe410000 0x0 0x1000>;
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
dmas = <&dmac1 2>, <&dmac1 3>;
|
dma-names = "tx", "rx";
|
resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
|
reset-names = "tx-m", "rx-m";
|
rockchip,cru = <&cru>;
|
rockchip,grf = <&grf>;
|
#sound-dai-cells = <0>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&i2s1m0_sclktx
|
&i2s1m0_sclkrx
|
&i2s1m0_lrcktx
|
&i2s1m0_lrckrx
|
&i2s1m0_sdi0
|
&i2s1m0_sdi1
|
&i2s1m0_sdi2
|
&i2s1m0_sdi3
|
&i2s1m0_sdo0
|
&i2s1m0_sdo1
|
&i2s1m0_sdo2
|
&i2s1m0_sdo3>;
|
status = "disabled";
|
};
|
|
i2s2_2ch: i2s@fe420000 {
|
compatible = "rockchip,rk3568-i2s-tdm";
|
reg = <0x0 0xfe420000 0x0 0x1000>;
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
dmas = <&dmac1 4>, <&dmac1 5>;
|
dma-names = "tx", "rx";
|
rockchip,cru = <&cru>;
|
rockchip,grf = <&grf>;
|
rockchip,clk-trcm = <1>;
|
#sound-dai-cells = <0>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&i2s2m0_sclktx
|
&i2s2m0_lrcktx
|
&i2s2m0_sdi
|
&i2s2m0_sdo>;
|
status = "disabled";
|
};
|
|
i2s3_2ch: i2s@fe430000 {
|
compatible = "rockchip,rk3568-i2s-tdm";
|
reg = <0x0 0xfe430000 0x0 0x1000>;
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>;
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
dmas = <&dmac1 6>, <&dmac1 7>;
|
dma-names = "tx", "rx";
|
resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
|
reset-names = "tx-m", "rx-m";
|
rockchip,cru = <&cru>;
|
rockchip,grf = <&grf>;
|
rockchip,clk-trcm = <1>;
|
#sound-dai-cells = <0>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&i2s3m0_sclk
|
&i2s3m0_lrck
|
&i2s3m0_sdi
|
&i2s3m0_sdo>;
|
status = "disabled";
|
};
|
|
pdm: pdm@fe440000 {
|
compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
|
reg = <0x0 0xfe440000 0x0 0x1000>;
|
clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
|
clock-names = "pdm_clk", "pdm_hclk";
|
dmas = <&dmac1 9>;
|
dma-names = "rx";
|
pinctrl-names = "default";
|
pinctrl-0 = <&pdmm0_clk
|
&pdmm0_clk1
|
&pdmm0_sdi0
|
&pdmm0_sdi1
|
&pdmm0_sdi2
|
&pdmm0_sdi3>;
|
#sound-dai-cells = <0>;
|
status = "disabled";
|
};
|
|
vad: vad@fe450000 {
|
compatible = "rockchip,rk3568-vad";
|
reg = <0x0 0xfe450000 0x0 0x10000>;
|
reg-names = "vad";
|
clocks = <&cru HCLK_VAD>;
|
clock-names = "hclk";
|
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
rockchip,audio-src = <0>;
|
rockchip,det-channel = <0>;
|
rockchip,mode = <0>;
|
#sound-dai-cells = <0>;
|
status = "disabled";
|
};
|
|
spdif_8ch: spdif@fe460000 {
|
compatible = "rockchip,rk3568-spdif";
|
reg = <0x0 0xfe460000 0x0 0x1000>;
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
dmas = <&dmac1 1>;
|
dma-names = "tx";
|
clock-names = "mclk", "hclk";
|
clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
|
#sound-dai-cells = <0>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&spdifm0_tx>;
|
status = "disabled";
|
};
|
|
audpwm: audpwm@fe470000 {
|
compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1";
|
reg = <0x0 0xfe470000 0x0 0x1000>;
|
clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>;
|
clock-names = "clk", "hclk";
|
dmas = <&dmac1 8>;
|
dma-names = "tx";
|
#sound-dai-cells = <0>;
|
rockchip,sample-width-bits = <11>;
|
rockchip,interpolat-points = <1>;
|
status = "disabled";
|
};
|
|
dig_acodec: codec-digital@fe478000 {
|
compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1";
|
reg = <0x0 0xfe478000 0x0 0x1000>;
|
clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>,
|
<&cru CLK_ACDCDIG_I2C>, <&cru HCLK_ACDCDIG>;
|
clock-names = "adc", "dac", "i2c", "pclk";
|
pinctrl-names = "default";
|
pinctrl-0 = <&acodec_pins>;
|
resets = <&cru SRST_ACDCDIG>;
|
reset-names = "reset" ;
|
rockchip,grf = <&grf>;
|
#sound-dai-cells = <0>;
|
status = "disabled";
|
};
|
|
dmac0: dmac@fe530000 {
|
compatible = "arm,pl330", "arm,primecell";
|
reg = <0x0 0xfe530000 0x0 0x4000>;
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru ACLK_BUS>;
|
clock-names = "apb_pclk";
|
#dma-cells = <1>;
|
arm,pl330-periph-burst;
|
};
|
|
dmac1: dmac@fe550000 {
|
compatible = "arm,pl330", "arm,primecell";
|
reg = <0x0 0xfe550000 0x0 0x4000>;
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru ACLK_BUS>;
|
clock-names = "apb_pclk";
|
#dma-cells = <1>;
|
arm,pl330-periph-burst;
|
};
|
|
scr: rkscr@fe560000 {
|
compatible = "rockchip-scr";
|
reg = <0x0 0xfe560000 0x0 0x10000>;
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&scr_pins>;
|
clocks = <&cru PCLK_SCR>;
|
clock-names = "g_pclk_sim_card";
|
status = "disabled";
|
};
|
|
can0: can@fe570000 {
|
compatible = "rockchip,rk3568-can-2.0";
|
reg = <0x0 0xfe570000 0x0 0x1000>;
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
|
clock-names = "baudclk", "apb_pclk";
|
resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
|
reset-names = "can", "can-apb";
|
tx-fifo-depth = <1>;
|
rx-fifo-depth = <6>;
|
status = "disabled";
|
};
|
|
can1: can@fe580000 {
|
compatible = "rockchip,rk3568-can-2.0";
|
reg = <0x0 0xfe580000 0x0 0x1000>;
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
|
clock-names = "baudclk", "apb_pclk";
|
resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
|
reset-names = "can", "can-apb";
|
tx-fifo-depth = <1>;
|
rx-fifo-depth = <6>;
|
status = "disabled";
|
};
|
|
can2: can@fe590000 {
|
compatible = "rockchip,rk3568-can-2.0";
|
reg = <0x0 0xfe590000 0x0 0x1000>;
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
|
clock-names = "baudclk", "apb_pclk";
|
resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
|
reset-names = "can", "can-apb";
|
tx-fifo-depth = <1>;
|
rx-fifo-depth = <6>;
|
status = "disabled";
|
};
|
|
i2c1: i2c@fe5a0000 {
|
compatible = "rockchip,rk3399-i2c";
|
reg = <0x0 0xfe5a0000 0x0 0x1000>;
|
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
|
clock-names = "i2c", "pclk";
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&i2c1_xfer>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
status = "disabled";
|
};
|
|
i2c2: i2c@fe5b0000 {
|
compatible = "rockchip,rk3399-i2c";
|
reg = <0x0 0xfe5b0000 0x0 0x1000>;
|
clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
|
clock-names = "i2c", "pclk";
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&i2c2m0_xfer>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
status = "disabled";
|
};
|
|
i2c3: i2c@fe5c0000 {
|
compatible = "rockchip,rk3399-i2c";
|
reg = <0x0 0xfe5c0000 0x0 0x1000>;
|
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
|
clock-names = "i2c", "pclk";
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&i2c3m0_xfer>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
status = "disabled";
|
};
|
|
i2c4: i2c@fe5d0000 {
|
compatible = "rockchip,rk3399-i2c";
|
reg = <0x0 0xfe5d0000 0x0 0x1000>;
|
clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
|
clock-names = "i2c", "pclk";
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&i2c4m0_xfer>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
status = "disabled";
|
};
|
|
i2c5: i2c@fe5e0000 {
|
compatible = "rockchip,rk3399-i2c";
|
reg = <0x0 0xfe5e0000 0x0 0x1000>;
|
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
|
clock-names = "i2c", "pclk";
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&i2c5m0_xfer>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
status = "disabled";
|
};
|
|
rktimer: timer@fe5f0000 {
|
compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer";
|
reg = <0x0 0xfe5f0000 0x0 0x1000>;
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
|
clock-names = "pclk", "timer";
|
};
|
|
wdt: watchdog@fe600000 {
|
compatible = "snps,dw-wdt";
|
reg = <0x0 0xfe600000 0x0 0x100>;
|
clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
|
clock-names = "tclk", "pclk";
|
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
status = "okay";
|
};
|
|
spi0: spi@fe610000 {
|
compatible = "rockchip,rk3066-spi";
|
reg = <0x0 0xfe610000 0x0 0x1000>;
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
|
clock-names = "spiclk", "apb_pclk";
|
dmas = <&dmac0 20>, <&dmac0 21>;
|
dma-names = "tx", "rx";
|
pinctrl-names = "default", "high_speed";
|
pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
|
pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>;
|
num-cs = <2>;
|
status = "disabled";
|
};
|
|
spi1: spi@fe620000 {
|
compatible = "rockchip,rk3066-spi";
|
reg = <0x0 0xfe620000 0x0 0x1000>;
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
|
clock-names = "spiclk", "apb_pclk";
|
dmas = <&dmac0 22>, <&dmac0 23>;
|
dma-names = "tx", "rx";
|
pinctrl-names = "default", "high_speed";
|
pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
|
pinctrl-1 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins_hs>;
|
num-cs = <2>;
|
status = "disabled";
|
};
|
|
spi2: spi@fe630000 {
|
compatible = "rockchip,rk3066-spi";
|
reg = <0x0 0xfe630000 0x0 0x1000>;
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
|
clock-names = "spiclk", "apb_pclk";
|
dmas = <&dmac0 24>, <&dmac0 25>;
|
dma-names = "tx", "rx";
|
pinctrl-names = "default", "high_speed";
|
pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
|
pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>;
|
num-cs = <2>;
|
status = "disabled";
|
};
|
|
spi3: spi@fe640000 {
|
compatible = "rockchip,rk3066-spi";
|
reg = <0x0 0xfe640000 0x0 0x1000>;
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
|
clock-names = "spiclk", "apb_pclk";
|
dmas = <&dmac0 26>, <&dmac0 27>;
|
dma-names = "tx", "rx";
|
pinctrl-names = "default", "high_speed";
|
pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
|
pinctrl-1 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins_hs>;
|
num-cs = <2>;
|
status = "disabled";
|
};
|
|
uart1: serial@fe650000 {
|
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfe650000 0x0 0x100>;
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <2>;
|
reg-io-width = <4>;
|
dmas = <&dmac0 2>, <&dmac0 3>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&uart1m0_xfer>;
|
status = "disabled";
|
};
|
|
uart2: serial@fe660000 {
|
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfe660000 0x0 0x100>;
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <2>;
|
reg-io-width = <4>;
|
dmas = <&dmac0 4>, <&dmac0 5>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&uart2m0_xfer>;
|
status = "disabled";
|
};
|
|
uart3: serial@fe670000 {
|
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfe670000 0x0 0x100>;
|
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <2>;
|
reg-io-width = <4>;
|
dmas = <&dmac0 6>, <&dmac0 7>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&uart3m0_xfer>;
|
status = "disabled";
|
};
|
|
uart4: serial@fe680000 {
|
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfe680000 0x0 0x100>;
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <2>;
|
reg-io-width = <4>;
|
dmas = <&dmac0 8>, <&dmac0 9>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&uart4m0_xfer>;
|
status = "disabled";
|
};
|
|
uart5: serial@fe690000 {
|
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfe690000 0x0 0x100>;
|
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <2>;
|
reg-io-width = <4>;
|
dmas = <&dmac0 10>, <&dmac0 11>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&uart5m0_xfer>;
|
status = "disabled";
|
};
|
|
uart6: serial@fe6a0000 {
|
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfe6a0000 0x0 0x100>;
|
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <2>;
|
reg-io-width = <4>;
|
dmas = <&dmac0 12>, <&dmac0 13>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&uart6m0_xfer>;
|
status = "disabled";
|
};
|
|
uart7: serial@fe6b0000 {
|
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfe6b0000 0x0 0x100>;
|
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <2>;
|
reg-io-width = <4>;
|
dmas = <&dmac0 14>, <&dmac0 15>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&uart7m0_xfer>;
|
status = "disabled";
|
};
|
|
uart8: serial@fe6c0000 {
|
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfe6c0000 0x0 0x100>;
|
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <2>;
|
reg-io-width = <4>;
|
dmas = <&dmac0 16>, <&dmac0 17>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&uart8m0_xfer>;
|
status = "disabled";
|
};
|
|
uart9: serial@fe6d0000 {
|
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfe6d0000 0x0 0x100>;
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <2>;
|
reg-io-width = <4>;
|
dmas = <&dmac0 18>, <&dmac0 19>;
|
pinctrl-names = "default";
|
pinctrl-0 = <&uart9m0_xfer>;
|
status = "disabled";
|
};
|
|
pwm4: pwm@fe6e0000 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfe6e0000 0x0 0x10>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm4_pins>;
|
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm5: pwm@fe6e0010 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfe6e0010 0x0 0x10>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm5_pins>;
|
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm6: pwm@fe6e0020 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfe6e0020 0x0 0x10>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm6_pins>;
|
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm7: pwm@fe6e0030 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfe6e0030 0x0 0x10>;
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm7_pins>;
|
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm8: pwm@fe6f0000 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfe6f0000 0x0 0x10>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm8m0_pins>;
|
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm9: pwm@fe6f0010 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfe6f0010 0x0 0x10>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm9m0_pins>;
|
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm10: pwm@fe6f0020 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfe6f0020 0x0 0x10>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm10m0_pins>;
|
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm11: pwm@fe6f0030 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfe6f0030 0x0 0x10>;
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm11m0_pins>;
|
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm12: pwm@fe700000 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfe700000 0x0 0x10>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm12m0_pins>;
|
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm13: pwm@fe700010 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfe700010 0x0 0x10>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm13m0_pins>;
|
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm14: pwm@fe700020 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfe700020 0x0 0x10>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm14m0_pins>;
|
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
pwm15: pwm@fe700030 {
|
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfe700030 0x0 0x10>;
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
#pwm-cells = <3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <&pwm15m0_pins>;
|
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
};
|
|
tsadc: tsadc@fe710000 {
|
compatible = "rockchip,rk3568-tsadc";
|
reg = <0x0 0xfe710000 0x0 0x100>;
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
rockchip,grf = <&grf>;
|
clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
clock-names = "tsadc", "apb_pclk";
|
assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
|
assigned-clock-rates = <17000000>, <700000>;
|
resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
|
<&cru SRST_TSADCPHY>;
|
reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
|
#thermal-sensor-cells = <1>;
|
nvmem-cells = <&tsadc_trim_base>, <&tsadc_trim_base_frac>;
|
nvmem-cell-names = "trim_base", "trim_base_frac";
|
rockchip,hw-tshut-temp = <120000>;
|
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
pinctrl-names = "gpio", "otpout";
|
pinctrl-0 = <&tsadc_gpio_func>;
|
pinctrl-1 = <&tsadc_shutorg>;
|
#address-cells = <1>;
|
#size-cells = <0>;
|
status = "disabled";
|
|
tsadc@0 {
|
reg = <0>;
|
nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>;
|
nvmem-cell-names = "trim_l", "trim_h";
|
};
|
tsadc@1 {
|
reg = <1>;
|
nvmem-cells = <&gpu_tsadc_trim_l>, <&gpu_tsadc_trim_h>;
|
nvmem-cell-names = "trim_l", "trim_h";
|
};
|
};
|
|
saradc: saradc@fe720000 {
|
compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
|
reg = <0x0 0xfe720000 0x0 0x100>;
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
#io-channel-cells = <1>;
|
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
|
clock-names = "saradc", "apb_pclk";
|
resets = <&cru SRST_P_SARADC>;
|
reset-names = "saradc-apb";
|
status = "disabled";
|
};
|
|
mailbox: mailbox@fe780000 {
|
compatible = "rockchip,rk3568-mailbox",
|
"rockchip,rk3368-mailbox";
|
reg = <0x0 0xfe780000 0x0 0x1000>;
|
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru PCLK_MAILBOX>;
|
clock-names = "pclk_mailbox";
|
#mbox-cells = <1>;
|
status = "disabled";
|
};
|
|
combphy0_us: phy@fe820000 {
|
compatible = "rockchip,rk3568-naneng-combphy";
|
reg = <0x0 0xfe820000 0x0 0x100>;
|
#phy-cells = <1>;
|
clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
|
<&cru PCLK_PIPE>;
|
clock-names = "refclk", "apbclk", "pipe_clk";
|
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
|
assigned-clock-rates = <100000000>;
|
resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
|
reset-names = "combphy-apb", "combphy";
|
rockchip,pipe-grf = <&pipegrf>;
|
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
|
status = "disabled";
|
};
|
|
combphy1_usq: phy@fe830000 {
|
compatible = "rockchip,rk3568-naneng-combphy";
|
reg = <0x0 0xfe830000 0x0 0x100>;
|
#phy-cells = <1>;
|
clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>,
|
<&cru PCLK_PIPE>;
|
clock-names = "refclk", "apbclk", "pipe_clk";
|
assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
|
assigned-clock-rates = <100000000>;
|
resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
|
reset-names = "combphy-apb", "combphy";
|
rockchip,pipe-grf = <&pipegrf>;
|
rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
|
status = "disabled";
|
};
|
|
combphy2_psq: phy@fe840000 {
|
compatible = "rockchip,rk3568-naneng-combphy";
|
reg = <0x0 0xfe840000 0x0 0x100>;
|
#phy-cells = <1>;
|
clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>,
|
<&cru PCLK_PIPE>;
|
clock-names = "refclk", "apbclk", "pipe_clk";
|
assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
|
assigned-clock-rates = <100000000>;
|
resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
|
reset-names = "combphy-apb", "combphy";
|
rockchip,pipe-grf = <&pipegrf>;
|
rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
|
status = "disabled";
|
};
|
|
video_phy0: phy@fe850000 {
|
compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
|
reg = <0x0 0xfe850000 0x0 0x10000>,
|
<0x0 0xfe060000 0x0 0x10000>;
|
reg-names = "phy", "host";
|
clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
|
<&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
|
clock-names = "ref", "pclk", "pclk_host";
|
#clock-cells = <0>;
|
resets = <&cru SRST_P_MIPIDSIPHY0>;
|
reset-names = "apb";
|
power-domains = <&power RK3568_PD_VO>;
|
#phy-cells = <0>;
|
status = "disabled";
|
};
|
|
video_phy1: phy@fe860000 {
|
compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
|
reg = <0x0 0xfe860000 0x0 0x10000>,
|
<0x0 0xfe070000 0x0 0x10000>;
|
reg-names = "phy", "host";
|
clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
|
<&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
|
clock-names = "ref", "pclk", "pclk_host";
|
#clock-cells = <0>;
|
resets = <&cru SRST_P_MIPIDSIPHY1>;
|
reset-names = "apb";
|
power-domains = <&power RK3568_PD_VO>;
|
#phy-cells = <0>;
|
status = "disabled";
|
};
|
|
csi2_dphy_hw: csi2-dphy-hw@fe870000 {
|
compatible = "rockchip,rk3568-csi2-dphy-hw";
|
reg = <0x0 0xfe870000 0x0 0x1000>;
|
clocks = <&cru PCLK_MIPICSIPHY>;
|
clock-names = "pclk";
|
rockchip,grf = <&grf>;
|
status = "disabled";
|
};
|
|
/*
|
* csi2_dphy0: used for csi2 dphy full mode,
|
is mutually exclusive with
|
csi2_dphy1 and csi2_dphy2
|
* csi2_dphy1: used for csi2 dphy split mode,
|
physical lanes use lane0 and lane1,
|
can be used with csi2_dphy2 parallel
|
* csi2_dphy2: used for csi2 dphy split mode,
|
physical lanes use lane2 and lane3,
|
can be used with csi2_dphy1 parallel
|
*/
|
csi2_dphy0: csi2-dphy0 {
|
compatible = "rockchip,rk3568-csi2-dphy";
|
rockchip,hw = <&csi2_dphy_hw>;
|
status = "disabled";
|
};
|
|
csi2_dphy1: csi2-dphy1 {
|
compatible = "rockchip,rk3568-csi2-dphy";
|
rockchip,hw = <&csi2_dphy_hw>;
|
status = "disabled";
|
};
|
|
csi2_dphy2: csi2-dphy2 {
|
compatible = "rockchip,rk3568-csi2-dphy";
|
rockchip,hw = <&csi2_dphy_hw>;
|
status = "disabled";
|
};
|
|
usb2phy0: usb2-phy@fe8a0000 {
|
compatible = "rockchip,rk3568-usb2phy";
|
reg = <0x0 0xfe8a0000 0x0 0x10000>;
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&pmucru CLK_USBPHY0_REF>;
|
clock-names = "phyclk";
|
#clock-cells = <0>;
|
assigned-clocks = <&cru USB480M>;
|
assigned-clock-parents = <&usb2phy0>;
|
clock-output-names = "usb480m_phy";
|
rockchip,usbgrf = <&usb2phy0_grf>;
|
status = "disabled";
|
|
u2phy0_host: host-port {
|
#phy-cells = <0>;
|
status = "disabled";
|
};
|
|
u2phy0_otg: otg-port {
|
#phy-cells = <0>;
|
status = "disabled";
|
};
|
};
|
|
usb2phy1: usb2-phy@fe8b0000 {
|
compatible = "rockchip,rk3568-usb2phy";
|
reg = <0x0 0xfe8b0000 0x0 0x10000>;
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&pmucru CLK_USBPHY1_REF>;
|
clock-names = "phyclk";
|
#clock-cells = <0>;
|
rockchip,usbgrf = <&usb2phy1_grf>;
|
status = "disabled";
|
|
u2phy1_host: host-port {
|
#phy-cells = <0>;
|
status = "disabled";
|
};
|
|
u2phy1_otg: otg-port {
|
#phy-cells = <0>;
|
status = "disabled";
|
};
|
};
|
|
pcie30phy: phy@fe8c0000 {
|
compatible = "rockchip,rk3568-pcie3-phy";
|
reg = <0x0 0xfe8c0000 0x0 0x20000>;
|
#phy-cells = <0>;
|
clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
|
<&cru PCLK_PCIE30PHY>;
|
clock-names = "refclk_m", "refclk_n", "pclk";
|
resets = <&cru SRST_PCIE30PHY>;
|
reset-names = "phy";
|
rockchip,phy-grf = <&pcie30_phy_grf>;
|
status = "disabled";
|
};
|
|
pinctrl: pinctrl {
|
compatible = "rockchip,rk3568-pinctrl";
|
rockchip,grf = <&grf>;
|
rockchip,pmu = <&pmugrf>;
|
#address-cells = <2>;
|
#size-cells = <2>;
|
ranges;
|
|
gpio0: gpio0@fdd60000 {
|
compatible = "rockchip,gpio-bank";
|
reg = <0x0 0xfdd60000 0x0 0x100>;
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
|
|
gpio-controller;
|
#gpio-cells = <2>;
|
interrupt-controller;
|
#interrupt-cells = <2>;
|
};
|
|
gpio1: gpio1@fe740000 {
|
compatible = "rockchip,gpio-bank";
|
reg = <0x0 0xfe740000 0x0 0x100>;
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
|
gpio-controller;
|
#gpio-cells = <2>;
|
interrupt-controller;
|
#interrupt-cells = <2>;
|
};
|
|
gpio2: gpio2@fe750000 {
|
compatible = "rockchip,gpio-bank";
|
reg = <0x0 0xfe750000 0x0 0x100>;
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
|
gpio-controller;
|
#gpio-cells = <2>;
|
interrupt-controller;
|
#interrupt-cells = <2>;
|
};
|
|
gpio3: gpio3@fe760000 {
|
compatible = "rockchip,gpio-bank";
|
reg = <0x0 0xfe760000 0x0 0x100>;
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
|
gpio-controller;
|
#gpio-cells = <2>;
|
interrupt-controller;
|
#interrupt-cells = <2>;
|
};
|
|
gpio4: gpio4@fe770000 {
|
compatible = "rockchip,gpio-bank";
|
reg = <0x0 0xfe770000 0x0 0x100>;
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
|
gpio-controller;
|
#gpio-cells = <2>;
|
interrupt-controller;
|
#interrupt-cells = <2>;
|
};
|
};
|
};
|
|
#include "rk3568-pinctrl.dtsi"
|
