/*
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* Allwinner DE2 display driver
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*
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* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <display.h>
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#include <dm.h>
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#include <edid.h>
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#include <video.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/display2.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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/* Maximum LCD size we support */
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LCD_MAX_WIDTH = 3840,
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LCD_MAX_HEIGHT = 2160,
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LCD_MAX_LOG2_BPP = VIDEO_BPP32,
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};
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static void sunxi_de2_composer_init(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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#ifdef CONFIG_MACH_SUN50I
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u32 reg_value;
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/* set SRAM for video use (A64 only) */
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reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
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reg_value &= ~(0x01 << 24);
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writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
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#endif
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clock_set_pll10(432000000);
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/* Set DE parent to pll10 */
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clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
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CCM_DE2_CTRL_PLL10);
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/* Set ahb gating to pass */
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setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
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setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
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/* Clock on */
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setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE);
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}
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static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
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int bpp, ulong address, bool is_composite)
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{
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ulong de_mux_base = (mux == 0) ?
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SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
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struct de_clk * const de_clk_regs =
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(struct de_clk *)(SUNXI_DE2_BASE);
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struct de_glb * const de_glb_regs =
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(struct de_glb *)(de_mux_base +
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SUNXI_DE2_MUX_GLB_REGS);
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struct de_bld * const de_bld_regs =
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(struct de_bld *)(de_mux_base +
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SUNXI_DE2_MUX_BLD_REGS);
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struct de_ui * const de_ui_regs =
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(struct de_ui *)(de_mux_base +
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SUNXI_DE2_MUX_CHAN_REGS +
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SUNXI_DE2_MUX_CHAN_SZ * 1);
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struct de_csc * const de_csc_regs =
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(struct de_csc *)(de_mux_base +
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SUNXI_DE2_MUX_DCSC_REGS);
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u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
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int channel;
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u32 format;
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/* enable clock */
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#ifdef CONFIG_MACH_SUN8I_H3
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setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);
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#else
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setbits_le32(&de_clk_regs->rst_cfg, BIT(mux));
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#endif
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setbits_le32(&de_clk_regs->gate_cfg, BIT(mux));
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setbits_le32(&de_clk_regs->bus_cfg, BIT(mux));
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clrbits_le32(&de_clk_regs->sel_cfg, 1);
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writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl);
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writel(0, &de_glb_regs->status);
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writel(1, &de_glb_regs->dbuff);
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writel(size, &de_glb_regs->size);
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for (channel = 0; channel < 4; channel++) {
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void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS +
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SUNXI_DE2_MUX_CHAN_SZ * channel);
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memset(ch, 0, (channel == 0) ?
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sizeof(struct de_vi) : sizeof(struct de_ui));
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}
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memset(de_bld_regs, 0, sizeof(struct de_bld));
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writel(0x00000101, &de_bld_regs->fcolor_ctl);
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writel(1, &de_bld_regs->route);
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writel(0, &de_bld_regs->premultiply);
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writel(0xff000000, &de_bld_regs->bkcolor);
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writel(0x03010301, &de_bld_regs->bld_mode[0]);
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writel(size, &de_bld_regs->output_size);
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writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0,
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&de_bld_regs->out_ctl);
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writel(0, &de_bld_regs->ck_ctl);
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writel(0xff000000, &de_bld_regs->attr[0].fcolor);
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writel(size, &de_bld_regs->attr[0].insize);
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/* Disable all other units */
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writel(0, de_mux_base + SUNXI_DE2_MUX_VSU_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_GSU1_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_GSU2_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_GSU3_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_FCE_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_BWS_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_LTI_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
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if (is_composite) {
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/* set CSC coefficients */
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writel(0x107, &de_csc_regs->coef11);
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writel(0x204, &de_csc_regs->coef12);
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writel(0x64, &de_csc_regs->coef13);
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writel(0x4200, &de_csc_regs->coef14);
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writel(0x1f68, &de_csc_regs->coef21);
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writel(0x1ed6, &de_csc_regs->coef22);
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writel(0x1c2, &de_csc_regs->coef23);
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writel(0x20200, &de_csc_regs->coef24);
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writel(0x1c2, &de_csc_regs->coef31);
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writel(0x1e87, &de_csc_regs->coef32);
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writel(0x1fb7, &de_csc_regs->coef33);
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writel(0x20200, &de_csc_regs->coef34);
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/* enable CSC unit */
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writel(1, &de_csc_regs->csc_ctl);
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} else {
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writel(0, &de_csc_regs->csc_ctl);
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}
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switch (bpp) {
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case 16:
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format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_RGB_565);
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break;
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case 32:
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default:
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format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888);
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break;
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}
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writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr);
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writel(size, &de_ui_regs->cfg[0].size);
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writel(0, &de_ui_regs->cfg[0].coord);
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writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch);
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writel(address, &de_ui_regs->cfg[0].top_laddr);
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writel(size, &de_ui_regs->ovl_size);
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/* apply settings */
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writel(1, &de_glb_regs->dbuff);
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}
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static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
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enum video_log2_bpp l2bpp,
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struct udevice *disp, int mux, bool is_composite)
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{
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct display_timing timing;
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struct display_plat *disp_uc_plat;
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int ret;
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disp_uc_plat = dev_get_uclass_platdata(disp);
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debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
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if (display_in_use(disp)) {
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debug(" - device in use\n");
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return -EBUSY;
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}
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disp_uc_plat->source_id = mux;
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ret = device_probe(disp);
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if (ret) {
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debug("%s: device '%s' display won't probe (ret=%d)\n",
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__func__, dev->name, ret);
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return ret;
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}
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ret = display_read_timing(disp, &timing);
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if (ret) {
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debug("%s: Failed to read timings\n", __func__);
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return ret;
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}
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sunxi_de2_composer_init();
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sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);
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ret = display_enable(disp, 1 << l2bpp, &timing);
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if (ret) {
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debug("%s: Failed to enable display\n", __func__);
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return ret;
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}
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uc_priv->xsize = timing.hactive.typ;
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uc_priv->ysize = timing.vactive.typ;
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uc_priv->bpix = l2bpp;
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debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
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return 0;
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}
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static int sunxi_de2_probe(struct udevice *dev)
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{
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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struct udevice *disp;
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int ret;
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/* Before relocation we don't need to do anything */
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if (!(gd->flags & GD_FLG_RELOC))
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return 0;
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ret = uclass_find_device_by_name(UCLASS_DISPLAY,
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"sunxi_dw_hdmi", &disp);
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if (!ret) {
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int mux;
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if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
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mux = 0;
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else
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mux = 1;
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ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
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false);
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if (!ret) {
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video_set_flush_dcache(dev, 1);
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return 0;
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}
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}
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debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
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ret = uclass_find_device_by_name(UCLASS_DISPLAY,
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"sunxi_tve", &disp);
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if (ret) {
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debug("%s: tv not found (ret=%d)\n", __func__, ret);
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return ret;
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}
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ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true);
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if (ret)
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return ret;
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video_set_flush_dcache(dev, 1);
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return 0;
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}
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static int sunxi_de2_bind(struct udevice *dev)
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{
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
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(1 << LCD_MAX_LOG2_BPP) / 8;
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return 0;
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}
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static const struct video_ops sunxi_de2_ops = {
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};
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U_BOOT_DRIVER(sunxi_de2) = {
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.name = "sunxi_de2",
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.id = UCLASS_VIDEO,
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.ops = &sunxi_de2_ops,
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.bind = sunxi_de2_bind,
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.probe = sunxi_de2_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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U_BOOT_DEVICE(sunxi_de2) = {
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.name = "sunxi_de2"
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};
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