/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
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* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/sizes.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <lcd.h>
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#include <atmel_lcdc.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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#include <netdev.h>
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#include <asm/mach-types.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_CMD_NAND
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static void pm9263_nand_hw_init(void)
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{
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unsigned long csa;
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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/* Enable CS3 */
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csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa[0]);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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/* Configure RDY/BSY */
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gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
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/* Enable NandFlash */
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gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif
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#ifdef CONFIG_MACB
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static void pm9263_macb_hw_init(void)
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{
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/*
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* PB27 enables the 50MHz oscillator for Ethernet PHY
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* 1 - enable
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* 0 - disable
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*/
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at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
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at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
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at91_periph_clk_enable(ATMEL_ID_EMAC);
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/*
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* Disable pull-up on:
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* RXDV (PC25) => PHY normal mode (not Test mode)
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* ERX0 (PE25) => PHY ADDR0
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* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
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*
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* PHY has internal pull-down
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*/
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at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
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at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
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at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
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/* Re-enable pull-up */
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at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
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at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
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at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
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at91_macb_hw_init();
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}
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#endif
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#ifdef CONFIG_LCD
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vidinfo_t panel_info = {
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.vl_col = 240,
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.vl_row = 320,
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.vl_clk = 4965000,
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.vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
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ATMEL_LCDC_INVFRAME_INVERTED,
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.vl_bpix = 3,
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.vl_tft = 1,
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.vl_hsync_len = 5,
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.vl_left_margin = 1,
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.vl_right_margin = 33,
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.vl_vsync_len = 1,
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.vl_upper_margin = 1,
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.vl_lower_margin = 0,
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.mmio = ATMEL_BASE_LCDC,
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};
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void lcd_enable(void)
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{
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at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
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}
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#ifdef CONFIG_LCD_IN_PSRAM
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#define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
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#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
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/* Initialize the PSRAM memory */
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static int pm9263_lcd_hw_psram_init(void)
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{
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unsigned long csa;
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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/* Enable CS3 3.3v, no pull-ups */
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csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
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AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
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writel(csa, &matrix->csa[1]);
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/* Configure SMC1 CS0 for PSRAM - 16-bit */
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writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[0].setup);
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writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
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AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
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&smc->cs[0].pulse);
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writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
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&smc->cs[0].cycle);
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writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
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&smc->cs[0].mode);
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/* setup PB29 as output */
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at91_set_pio_output(PSRAM_CRE_PIN, 1);
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at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
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/* PSRAM: write BCR */
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readw(PSRAM_CTRL_REG);
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readw(PSRAM_CTRL_REG);
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writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
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writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
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/* write RCR of the PSRAM */
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readw(PSRAM_CTRL_REG);
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readw(PSRAM_CTRL_REG);
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writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
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/* set RCR; 0x10-async mode,0x90-page mode */
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writew(0x90, PSRAM_CTRL_REG);
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/*
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* test to see if the PSRAM is MT45W2M16A or MT45W2M16B
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* MT45W2M16B - CRE must be 0
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* MT45W2M16A - CRE must be 1
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*/
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writew(0x1234, PHYS_PSRAM);
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writew(0x5678, PHYS_PSRAM + 2);
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/* test if the chip is MT45W2M16B */
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if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
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/* try with CRE=1 (MT45W2M16A) */
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at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
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/* write RCR of the PSRAM */
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readw(PSRAM_CTRL_REG);
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readw(PSRAM_CTRL_REG);
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writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
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/* set RCR;0x10-async mode,0x90-page mode */
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writew(0x90, PSRAM_CTRL_REG);
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writew(0x1234, PHYS_PSRAM);
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writew(0x5678, PHYS_PSRAM+2);
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if ((readw(PHYS_PSRAM) != 0x1234)
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|| (readw(PHYS_PSRAM + 2) != 0x5678))
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return 1;
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}
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/* Bus matrix */
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writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
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writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
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return 0;
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}
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#endif
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static void pm9263_lcd_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
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at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
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at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
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at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
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at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
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at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
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at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
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at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
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at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
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at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
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at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
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at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
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at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
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at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
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at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
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at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
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at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
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at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
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at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
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at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
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at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
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at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
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at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
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at91_periph_clk_enable(ATMEL_ID_LCDC);
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/* Power Control */
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at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
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at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
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#ifdef CONFIG_LCD_IN_PSRAM
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/* initialize te PSRAM */
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int stat = pm9263_lcd_hw_psram_init();
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gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
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#else
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gd->fb_base = ATMEL_BASE_SRAM0;
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#endif
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}
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#ifdef CONFIG_LCD_INFO
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#include <nand.h>
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#include <version.h>
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extern flash_info_t flash_info[];
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void lcd_show_board_info(void)
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{
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ulong dram_size, nand_size, flash_size;
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int i;
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char temp[32];
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lcd_printf ("%s\n", U_BOOT_VERSION);
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lcd_printf ("(C) 2009 Ronetix GmbH\n");
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lcd_printf ("support@ronetix.at\n");
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lcd_printf ("%s CPU at %s MHz",
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CONFIG_SYS_AT91_CPU_NAME,
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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dram_size += gd->bd->bi_dram[i].size;
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nand_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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nand_size += get_nand_dev_by_index(i)->size;
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flash_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
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flash_size += flash_info[i].size;
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lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
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"4 MB PSRAM\n",
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dram_size >> 20,
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nand_size >> 20,
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flash_size >> 20);
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}
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#endif /* CONFIG_LCD_INFO */
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#endif /* CONFIG_LCD */
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int board_early_init_f(void)
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{
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return 0;
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}
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int board_init(void)
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{
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/* arch number of AT91SAM9263EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_PM9263;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_CMD_NAND
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pm9263_nand_hw_init();
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#endif
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#ifdef CONFIG_MACB
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pm9263_macb_hw_init();
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#endif
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#ifdef CONFIG_USB_OHCI_NEW
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at91_uhp_hw_init();
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#endif
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#ifdef CONFIG_LCD
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pm9263_lcd_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
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PHYS_SDRAM_SIZE);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
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#endif
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return rc;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard (void)
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{
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char *ss;
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printf ("Board : Ronetix PM9263\n");
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switch (gd->fb_base) {
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case PHYS_PSRAM:
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ss = "(PSRAM)";
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break;
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case ATMEL_BASE_SRAM0:
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ss = "(Internal SRAM)";
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break;
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default:
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ss = "";
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break;
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}
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printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
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printf ("\n");
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return 0;
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}
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#endif
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