/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <asm/io.h>
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#include <asm/arch/at91sam9261.h>
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#include <asm/arch/at91sam9261_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <lcd.h>
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#include <atmel_lcdc.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
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#include <net.h>
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#include <netdev.h>
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#endif
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#include <asm/mach-types.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_CMD_NAND
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static void at91sam9261ek_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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unsigned long csa;
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/* Enable CS3 */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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#ifdef CONFIG_AT91SAM9G10EK
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writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
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&smc->cs[3].cycle);
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#else
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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#endif
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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at91_periph_clk_enable(ATMEL_ID_PIOC);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
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at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
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}
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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static void at91sam9261ek_dm9000_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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/* Configure SMC CS2 for DM9000 */
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#ifdef CONFIG_AT91SAM9G10EK
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writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[2].setup);
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writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
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AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
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&smc->cs[2].pulse);
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writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
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&smc->cs[2].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
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AT91_SMC_MODE_TDF_CYCLE(1),
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&smc->cs[2].mode);
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#else
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writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[2].setup);
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
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AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
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&smc->cs[2].pulse);
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writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
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&smc->cs[2].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
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AT91_SMC_MODE_TDF_CYCLE(1),
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&smc->cs[2].mode);
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#endif
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/* Configure Reset signal as output */
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at91_set_gpio_output(AT91_PIN_PC10, 0);
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/* Configure Interrupt pin as input, no pull-up */
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at91_set_gpio_input(AT91_PIN_PC11, 0);
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}
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#endif
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#ifdef CONFIG_LCD
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vidinfo_t panel_info = {
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.vl_col = 240,
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.vl_row = 320,
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.vl_clk = 4965000,
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.vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
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ATMEL_LCDC_INVFRAME_INVERTED,
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.vl_bpix = 3,
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.vl_tft = 1,
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.vl_hsync_len = 5,
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.vl_left_margin = 1,
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.vl_right_margin = 33,
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.vl_vsync_len = 1,
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.vl_upper_margin = 1,
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.vl_lower_margin = 0,
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.mmio = ATMEL_BASE_LCDC,
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};
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void lcd_enable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
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}
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static void at91sam9261ek_lcd_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
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at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
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at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
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at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
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at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
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at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
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at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
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at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
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at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
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at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
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at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
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at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
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at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
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at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
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at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
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at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
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at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
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at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
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at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
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at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
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at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
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at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
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at91_system_clk_enable(AT91_PMC_HCK1);
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/* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
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#ifdef CONFIG_AT91SAM9261EK
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gd->fb_base = ATMEL_BASE_SRAM;
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#endif
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}
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#ifdef CONFIG_LCD_INFO
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#include <nand.h>
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#include <version.h>
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void lcd_show_board_info(void)
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{
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ulong dram_size, nand_size;
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int i;
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char temp[32];
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lcd_printf ("%s\n", U_BOOT_VERSION);
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lcd_printf ("(C) 2008 ATMEL Corp\n");
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lcd_printf ("at91support@atmel.com\n");
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lcd_printf ("%s CPU at %s MHz\n",
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ATMEL_CPU_NAME,
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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dram_size += gd->bd->bi_dram[i].size;
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nand_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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nand_size += get_nand_dev_by_index(i)->size;
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lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
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dram_size >> 20,
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nand_size >> 20 );
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}
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#endif /* CONFIG_LCD_INFO */
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#endif
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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at91_seriald_hw_init();
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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#endif
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return 0;
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}
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#endif
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int board_init(void)
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{
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#ifdef CONFIG_AT91SAM9G10EK
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/* arch number of AT91SAM9G10EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
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#else
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/* arch number of AT91SAM9261EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
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#endif
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_CMD_NAND
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at91sam9261ek_nand_hw_init();
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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at91sam9261ek_dm9000_hw_init();
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#endif
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#ifdef CONFIG_LCD
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at91sam9261ek_lcd_hw_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_DRIVER_DM9000
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int board_eth_init(bd_t *bis)
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{
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return dm9000_initialize(bis);
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}
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#endif
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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#ifdef CONFIG_DRIVER_DM9000
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/*
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* Initialize ethernet HW addr prior to starting Linux,
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* needed for nfsroot
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*/
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eth_init();
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#endif
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}
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#endif
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