// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <linux/regmap.h>
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#include <linux/thermal.h>
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#include "tsens.h"
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#define CAL_MDEGC 30000
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#define CONFIG_ADDR 0x3640
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#define CONFIG_ADDR_8660 0x3620
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/* CONFIG_ADDR bitmasks */
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#define CONFIG 0x9b
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#define CONFIG_MASK 0xf
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#define CONFIG_8660 1
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#define CONFIG_SHIFT_8660 28
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#define CONFIG_MASK_8660 (3 << CONFIG_SHIFT_8660)
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#define STATUS_CNTL_ADDR_8064 0x3660
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#define CNTL_ADDR 0x3620
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/* CNTL_ADDR bitmasks */
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#define EN BIT(0)
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#define SW_RST BIT(1)
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#define SENSOR0_EN BIT(3)
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#define SLP_CLK_ENA BIT(26)
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#define SLP_CLK_ENA_8660 BIT(24)
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#define MEASURE_PERIOD 1
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#define SENSOR0_SHIFT 3
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/* INT_STATUS_ADDR bitmasks */
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#define MIN_STATUS_MASK BIT(0)
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#define LOWER_STATUS_CLR BIT(1)
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#define UPPER_STATUS_CLR BIT(2)
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#define MAX_STATUS_MASK BIT(3)
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#define THRESHOLD_ADDR 0x3624
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/* THRESHOLD_ADDR bitmasks */
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#define THRESHOLD_MAX_LIMIT_SHIFT 24
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#define THRESHOLD_MIN_LIMIT_SHIFT 16
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#define THRESHOLD_UPPER_LIMIT_SHIFT 8
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#define THRESHOLD_LOWER_LIMIT_SHIFT 0
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/* Initial temperature threshold values */
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#define LOWER_LIMIT_TH 0x50
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#define UPPER_LIMIT_TH 0xdf
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#define MIN_LIMIT_TH 0x0
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#define MAX_LIMIT_TH 0xff
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#define S0_STATUS_ADDR 0x3628
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#define INT_STATUS_ADDR 0x363c
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#define TRDY_MASK BIT(7)
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#define TIMEOUT_US 100
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static int suspend_8960(struct tsens_priv *priv)
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{
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int ret;
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unsigned int mask;
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struct regmap *map = priv->tm_map;
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ret = regmap_read(map, THRESHOLD_ADDR, &priv->ctx.threshold);
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if (ret)
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return ret;
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ret = regmap_read(map, CNTL_ADDR, &priv->ctx.control);
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if (ret)
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return ret;
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if (priv->num_sensors > 1)
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mask = SLP_CLK_ENA | EN;
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else
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mask = SLP_CLK_ENA_8660 | EN;
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ret = regmap_update_bits(map, CNTL_ADDR, mask, 0);
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if (ret)
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return ret;
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return 0;
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}
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static int resume_8960(struct tsens_priv *priv)
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{
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int ret;
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struct regmap *map = priv->tm_map;
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ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST);
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if (ret)
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return ret;
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/*
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* Separate CONFIG restore is not needed only for 8660 as
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* config is part of CTRL Addr and its restored as such
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*/
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if (priv->num_sensors > 1) {
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ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG);
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if (ret)
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return ret;
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}
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ret = regmap_write(map, THRESHOLD_ADDR, priv->ctx.threshold);
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if (ret)
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return ret;
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ret = regmap_write(map, CNTL_ADDR, priv->ctx.control);
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if (ret)
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return ret;
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return 0;
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}
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static int enable_8960(struct tsens_priv *priv, int id)
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{
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int ret;
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u32 reg, mask;
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ret = regmap_read(priv->tm_map, CNTL_ADDR, ®);
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if (ret)
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return ret;
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mask = BIT(id + SENSOR0_SHIFT);
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ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST);
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if (ret)
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return ret;
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if (priv->num_sensors > 1)
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reg |= mask | SLP_CLK_ENA | EN;
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else
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reg |= mask | SLP_CLK_ENA_8660 | EN;
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ret = regmap_write(priv->tm_map, CNTL_ADDR, reg);
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if (ret)
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return ret;
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return 0;
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}
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static void disable_8960(struct tsens_priv *priv)
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{
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int ret;
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u32 reg_cntl;
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u32 mask;
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mask = GENMASK(priv->num_sensors - 1, 0);
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mask <<= SENSOR0_SHIFT;
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mask |= EN;
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ret = regmap_read(priv->tm_map, CNTL_ADDR, ®_cntl);
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if (ret)
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return;
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reg_cntl &= ~mask;
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if (priv->num_sensors > 1)
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reg_cntl &= ~SLP_CLK_ENA;
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else
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reg_cntl &= ~SLP_CLK_ENA_8660;
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regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
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}
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static int init_8960(struct tsens_priv *priv)
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{
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int ret, i;
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u32 reg_cntl;
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priv->tm_map = dev_get_regmap(priv->dev, NULL);
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if (!priv->tm_map)
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return -ENODEV;
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/*
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* The status registers for each sensor are discontiguous
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* because some SoCs have 5 sensors while others have more
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* but the control registers stay in the same place, i.e
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* directly after the first 5 status registers.
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*/
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for (i = 0; i < priv->num_sensors; i++) {
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if (i >= 5)
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priv->sensor[i].status = S0_STATUS_ADDR + 40;
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priv->sensor[i].status += i * 4;
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}
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reg_cntl = SW_RST;
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ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl);
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if (ret)
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return ret;
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if (priv->num_sensors > 1) {
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reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
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reg_cntl &= ~SW_RST;
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ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR,
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CONFIG_MASK, CONFIG);
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} else {
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reg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16);
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reg_cntl &= ~CONFIG_MASK_8660;
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reg_cntl |= CONFIG_8660 << CONFIG_SHIFT_8660;
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}
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reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;
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ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
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if (ret)
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return ret;
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reg_cntl |= EN;
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ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
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if (ret)
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return ret;
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return 0;
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}
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static int calibrate_8960(struct tsens_priv *priv)
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{
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int i;
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char *data;
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ssize_t num_read = priv->num_sensors;
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struct tsens_sensor *s = priv->sensor;
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data = qfprom_read(priv->dev, "calib");
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if (IS_ERR(data))
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data = qfprom_read(priv->dev, "calib_backup");
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if (IS_ERR(data))
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return PTR_ERR(data);
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for (i = 0; i < num_read; i++, s++)
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s->offset = data[i];
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kfree(data);
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return 0;
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}
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/* Temperature on y axis and ADC-code on x-axis */
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static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s)
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{
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int slope, offset;
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slope = thermal_zone_get_slope(s->tzd);
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offset = CAL_MDEGC - slope * s->offset;
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return adc_code * slope + offset;
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}
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static int get_temp_8960(const struct tsens_sensor *s, int *temp)
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{
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int ret;
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u32 code, trdy;
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struct tsens_priv *priv = s->priv;
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unsigned long timeout;
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timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
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do {
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ret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy);
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if (ret)
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return ret;
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if (!(trdy & TRDY_MASK))
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continue;
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ret = regmap_read(priv->tm_map, s->status, &code);
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if (ret)
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return ret;
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*temp = code_to_mdegC(code, s);
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return 0;
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} while (time_before(jiffies, timeout));
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return -ETIMEDOUT;
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}
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static const struct tsens_ops ops_8960 = {
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.init = init_8960,
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.calibrate = calibrate_8960,
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.get_temp = get_temp_8960,
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.enable = enable_8960,
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.disable = disable_8960,
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.suspend = suspend_8960,
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.resume = resume_8960,
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};
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struct tsens_plat_data data_8960 = {
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.num_sensors = 11,
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.ops = &ops_8960,
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};
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