// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx 'Clocking Wizard' driver
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*
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* Copyright (C) 2013 - 2014 Xilinx
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*
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* Sören Brinkmann <soren.brinkmann@xilinx.com>
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*/
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#define WZRD_NUM_OUTPUTS 7
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#define WZRD_ACLK_MAX_FREQ 250000000UL
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#define WZRD_CLK_CFG_REG(n) (0x200 + 4 * (n))
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#define WZRD_CLKOUT0_FRAC_EN BIT(18)
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#define WZRD_CLKFBOUT_FRAC_EN BIT(26)
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#define WZRD_CLKFBOUT_MULT_SHIFT 8
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#define WZRD_CLKFBOUT_MULT_MASK (0xff << WZRD_CLKFBOUT_MULT_SHIFT)
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#define WZRD_DIVCLK_DIVIDE_SHIFT 0
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#define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
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#define WZRD_CLKOUT_DIVIDE_SHIFT 0
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#define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
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enum clk_wzrd_int_clks {
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wzrd_clk_mul,
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wzrd_clk_mul_div,
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wzrd_clk_int_max
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};
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/**
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* struct clk_wzrd:
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* @clk_data: Clock data
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* @nb: Notifier block
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* @base: Memory base
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* @clk_in1: Handle to input clock 'clk_in1'
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* @axi_clk: Handle to input clock 's_axi_aclk'
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* @clks_internal: Internal clocks
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* @clkout: Output clocks
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* @speed_grade: Speed grade of the device
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* @suspended: Flag indicating power state of the device
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*/
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struct clk_wzrd {
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struct clk_onecell_data clk_data;
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struct notifier_block nb;
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void __iomem *base;
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struct clk *clk_in1;
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struct clk *axi_clk;
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struct clk *clks_internal[wzrd_clk_int_max];
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struct clk *clkout[WZRD_NUM_OUTPUTS];
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unsigned int speed_grade;
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bool suspended;
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};
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#define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb)
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/* maximum frequencies for input/output clocks per speed grade */
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static const unsigned long clk_wzrd_max_freq[] = {
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800000000UL,
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933000000UL,
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1066000000UL
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};
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static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event,
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void *data)
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{
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unsigned long max;
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struct clk_notifier_data *ndata = data;
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struct clk_wzrd *clk_wzrd = to_clk_wzrd(nb);
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if (clk_wzrd->suspended)
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return NOTIFY_OK;
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if (ndata->clk == clk_wzrd->clk_in1)
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max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1];
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else if (ndata->clk == clk_wzrd->axi_clk)
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max = WZRD_ACLK_MAX_FREQ;
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else
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return NOTIFY_DONE; /* should never happen */
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switch (event) {
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case PRE_RATE_CHANGE:
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if (ndata->new_rate > max)
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return NOTIFY_BAD;
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return NOTIFY_OK;
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case POST_RATE_CHANGE:
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case ABORT_RATE_CHANGE:
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default:
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return NOTIFY_DONE;
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}
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}
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static int __maybe_unused clk_wzrd_suspend(struct device *dev)
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{
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struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
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clk_disable_unprepare(clk_wzrd->axi_clk);
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clk_wzrd->suspended = true;
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return 0;
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}
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static int __maybe_unused clk_wzrd_resume(struct device *dev)
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{
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int ret;
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struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
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ret = clk_prepare_enable(clk_wzrd->axi_clk);
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if (ret) {
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dev_err(dev, "unable to enable s_axi_aclk\n");
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return ret;
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}
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clk_wzrd->suspended = false;
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend,
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clk_wzrd_resume);
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static int clk_wzrd_probe(struct platform_device *pdev)
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{
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int i, ret;
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u32 reg;
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unsigned long rate;
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const char *clk_name;
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struct clk_wzrd *clk_wzrd;
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struct device_node *np = pdev->dev.of_node;
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clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL);
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if (!clk_wzrd)
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return -ENOMEM;
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platform_set_drvdata(pdev, clk_wzrd);
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clk_wzrd->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(clk_wzrd->base))
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return PTR_ERR(clk_wzrd->base);
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ret = of_property_read_u32(np, "speed-grade", &clk_wzrd->speed_grade);
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if (!ret) {
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if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) {
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dev_warn(&pdev->dev, "invalid speed grade '%d'\n",
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clk_wzrd->speed_grade);
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clk_wzrd->speed_grade = 0;
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}
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}
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clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1");
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if (IS_ERR(clk_wzrd->clk_in1)) {
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if (clk_wzrd->clk_in1 != ERR_PTR(-EPROBE_DEFER))
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dev_err(&pdev->dev, "clk_in1 not found\n");
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return PTR_ERR(clk_wzrd->clk_in1);
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}
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clk_wzrd->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
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if (IS_ERR(clk_wzrd->axi_clk)) {
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if (clk_wzrd->axi_clk != ERR_PTR(-EPROBE_DEFER))
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dev_err(&pdev->dev, "s_axi_aclk not found\n");
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return PTR_ERR(clk_wzrd->axi_clk);
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}
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ret = clk_prepare_enable(clk_wzrd->axi_clk);
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if (ret) {
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dev_err(&pdev->dev, "enabling s_axi_aclk failed\n");
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return ret;
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}
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rate = clk_get_rate(clk_wzrd->axi_clk);
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if (rate > WZRD_ACLK_MAX_FREQ) {
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dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n",
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rate);
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ret = -EINVAL;
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goto err_disable_clk;
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}
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/* we don't support fractional div/mul yet */
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reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
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WZRD_CLKFBOUT_FRAC_EN;
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reg |= readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2)) &
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WZRD_CLKOUT0_FRAC_EN;
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if (reg)
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dev_warn(&pdev->dev, "fractional div/mul not supported\n");
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/* register multiplier */
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reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
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WZRD_CLKFBOUT_MULT_MASK) >> WZRD_CLKFBOUT_MULT_SHIFT;
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clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev));
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if (!clk_name) {
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ret = -ENOMEM;
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goto err_disable_clk;
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}
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clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor
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(&pdev->dev, clk_name,
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__clk_get_name(clk_wzrd->clk_in1),
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0, reg, 1);
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kfree(clk_name);
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if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) {
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dev_err(&pdev->dev, "unable to register fixed-factor clock\n");
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ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]);
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goto err_disable_clk;
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}
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/* register div */
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reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
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WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT;
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clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
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if (!clk_name) {
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ret = -ENOMEM;
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goto err_rm_int_clk;
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}
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clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor
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(&pdev->dev, clk_name,
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__clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
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0, 1, reg);
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if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) {
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dev_err(&pdev->dev, "unable to register divider clock\n");
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ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]);
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goto err_rm_int_clk;
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}
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/* register div per output */
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for (i = WZRD_NUM_OUTPUTS - 1; i >= 0 ; i--) {
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const char *clkout_name;
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if (of_property_read_string_index(np, "clock-output-names", i,
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&clkout_name)) {
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dev_err(&pdev->dev,
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"clock output name not specified\n");
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ret = -EINVAL;
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goto err_rm_int_clks;
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}
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reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2) + i * 12);
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reg &= WZRD_CLKOUT_DIVIDE_MASK;
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reg >>= WZRD_CLKOUT_DIVIDE_SHIFT;
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clk_wzrd->clkout[i] = clk_register_fixed_factor
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(&pdev->dev, clkout_name, clk_name, 0, 1, reg);
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if (IS_ERR(clk_wzrd->clkout[i])) {
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int j;
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for (j = i + 1; j < WZRD_NUM_OUTPUTS; j++)
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clk_unregister(clk_wzrd->clkout[j]);
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dev_err(&pdev->dev,
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"unable to register divider clock\n");
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ret = PTR_ERR(clk_wzrd->clkout[i]);
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goto err_rm_int_clks;
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}
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}
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kfree(clk_name);
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clk_wzrd->clk_data.clks = clk_wzrd->clkout;
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clk_wzrd->clk_data.clk_num = ARRAY_SIZE(clk_wzrd->clkout);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_wzrd->clk_data);
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if (clk_wzrd->speed_grade) {
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clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier;
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ret = clk_notifier_register(clk_wzrd->clk_in1,
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&clk_wzrd->nb);
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if (ret)
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dev_warn(&pdev->dev,
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"unable to register clock notifier\n");
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ret = clk_notifier_register(clk_wzrd->axi_clk, &clk_wzrd->nb);
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if (ret)
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dev_warn(&pdev->dev,
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"unable to register clock notifier\n");
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}
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return 0;
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err_rm_int_clks:
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clk_unregister(clk_wzrd->clks_internal[1]);
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err_rm_int_clk:
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kfree(clk_name);
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clk_unregister(clk_wzrd->clks_internal[0]);
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err_disable_clk:
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clk_disable_unprepare(clk_wzrd->axi_clk);
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return ret;
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}
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static int clk_wzrd_remove(struct platform_device *pdev)
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{
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int i;
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struct clk_wzrd *clk_wzrd = platform_get_drvdata(pdev);
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of_clk_del_provider(pdev->dev.of_node);
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for (i = 0; i < WZRD_NUM_OUTPUTS; i++)
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clk_unregister(clk_wzrd->clkout[i]);
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for (i = 0; i < wzrd_clk_int_max; i++)
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clk_unregister(clk_wzrd->clks_internal[i]);
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if (clk_wzrd->speed_grade) {
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clk_notifier_unregister(clk_wzrd->axi_clk, &clk_wzrd->nb);
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clk_notifier_unregister(clk_wzrd->clk_in1, &clk_wzrd->nb);
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}
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clk_disable_unprepare(clk_wzrd->axi_clk);
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return 0;
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}
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static const struct of_device_id clk_wzrd_ids[] = {
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{ .compatible = "xlnx,clocking-wizard" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, clk_wzrd_ids);
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static struct platform_driver clk_wzrd_driver = {
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.driver = {
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.name = "clk-wizard",
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.of_match_table = clk_wzrd_ids,
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.pm = &clk_wzrd_dev_pm_ops,
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},
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.probe = clk_wzrd_probe,
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.remove = clk_wzrd_remove,
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};
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module_platform_driver(clk_wzrd_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com");
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MODULE_DESCRIPTION("Driver for the Xilinx Clocking Wizard IP core");
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