// SPDX-License-Identifier: GPL-2.0
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//
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// Freescale imx6ul pinctrl driver
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//
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// Author: Anson Huang <Anson.Huang@freescale.com>
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// Copyright (C) 2015 Freescale Semiconductor, Inc.
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-imx.h"
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enum imx6ul_pads {
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MX6UL_PAD_RESERVE0 = 0,
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MX6UL_PAD_RESERVE1 = 1,
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MX6UL_PAD_RESERVE2 = 2,
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MX6UL_PAD_RESERVE3 = 3,
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MX6UL_PAD_RESERVE4 = 4,
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MX6UL_PAD_RESERVE5 = 5,
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MX6UL_PAD_RESERVE6 = 6,
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MX6UL_PAD_RESERVE7 = 7,
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MX6UL_PAD_RESERVE8 = 8,
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MX6UL_PAD_RESERVE9 = 9,
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MX6UL_PAD_RESERVE10 = 10,
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MX6UL_PAD_SNVS_TAMPER4 = 11,
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MX6UL_PAD_RESERVE12 = 12,
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MX6UL_PAD_RESERVE13 = 13,
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MX6UL_PAD_RESERVE14 = 14,
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MX6UL_PAD_RESERVE15 = 15,
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MX6UL_PAD_RESERVE16 = 16,
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MX6UL_PAD_JTAG_MOD = 17,
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MX6UL_PAD_JTAG_TMS = 18,
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MX6UL_PAD_JTAG_TDO = 19,
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MX6UL_PAD_JTAG_TDI = 20,
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MX6UL_PAD_JTAG_TCK = 21,
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MX6UL_PAD_JTAG_TRST_B = 22,
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MX6UL_PAD_GPIO1_IO00 = 23,
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MX6UL_PAD_GPIO1_IO01 = 24,
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MX6UL_PAD_GPIO1_IO02 = 25,
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MX6UL_PAD_GPIO1_IO03 = 26,
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MX6UL_PAD_GPIO1_IO04 = 27,
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MX6UL_PAD_GPIO1_IO05 = 28,
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MX6UL_PAD_GPIO1_IO06 = 29,
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MX6UL_PAD_GPIO1_IO07 = 30,
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MX6UL_PAD_GPIO1_IO08 = 31,
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MX6UL_PAD_GPIO1_IO09 = 32,
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MX6UL_PAD_UART1_TX_DATA = 33,
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MX6UL_PAD_UART1_RX_DATA = 34,
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MX6UL_PAD_UART1_CTS_B = 35,
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MX6UL_PAD_UART1_RTS_B = 36,
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MX6UL_PAD_UART2_TX_DATA = 37,
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MX6UL_PAD_UART2_RX_DATA = 38,
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MX6UL_PAD_UART2_CTS_B = 39,
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MX6UL_PAD_UART2_RTS_B = 40,
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MX6UL_PAD_UART3_TX_DATA = 41,
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MX6UL_PAD_UART3_RX_DATA = 42,
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MX6UL_PAD_UART3_CTS_B = 43,
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MX6UL_PAD_UART3_RTS_B = 44,
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MX6UL_PAD_UART4_TX_DATA = 45,
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MX6UL_PAD_UART4_RX_DATA = 46,
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MX6UL_PAD_UART5_TX_DATA = 47,
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MX6UL_PAD_UART5_RX_DATA = 48,
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MX6UL_PAD_ENET1_RX_DATA0 = 49,
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MX6UL_PAD_ENET1_RX_DATA1 = 50,
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MX6UL_PAD_ENET1_RX_EN = 51,
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MX6UL_PAD_ENET1_TX_DATA0 = 52,
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MX6UL_PAD_ENET1_TX_DATA1 = 53,
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MX6UL_PAD_ENET1_TX_EN = 54,
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MX6UL_PAD_ENET1_TX_CLK = 55,
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MX6UL_PAD_ENET1_RX_ER = 56,
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MX6UL_PAD_ENET2_RX_DATA0 = 57,
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MX6UL_PAD_ENET2_RX_DATA1 = 58,
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MX6UL_PAD_ENET2_RX_EN = 59,
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MX6UL_PAD_ENET2_TX_DATA0 = 60,
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MX6UL_PAD_ENET2_TX_DATA1 = 61,
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MX6UL_PAD_ENET2_TX_EN = 62,
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MX6UL_PAD_ENET2_TX_CLK = 63,
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MX6UL_PAD_ENET2_RX_ER = 64,
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MX6UL_PAD_LCD_CLK = 65,
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MX6UL_PAD_LCD_ENABLE = 66,
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MX6UL_PAD_LCD_HSYNC = 67,
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MX6UL_PAD_LCD_VSYNC = 68,
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MX6UL_PAD_LCD_RESET = 69,
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MX6UL_PAD_LCD_DATA00 = 70,
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MX6UL_PAD_LCD_DATA01 = 71,
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MX6UL_PAD_LCD_DATA02 = 72,
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MX6UL_PAD_LCD_DATA03 = 73,
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MX6UL_PAD_LCD_DATA04 = 74,
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MX6UL_PAD_LCD_DATA05 = 75,
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MX6UL_PAD_LCD_DATA06 = 76,
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MX6UL_PAD_LCD_DATA07 = 77,
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MX6UL_PAD_LCD_DATA08 = 78,
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MX6UL_PAD_LCD_DATA09 = 79,
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MX6UL_PAD_LCD_DATA10 = 80,
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MX6UL_PAD_LCD_DATA11 = 81,
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MX6UL_PAD_LCD_DATA12 = 82,
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MX6UL_PAD_LCD_DATA13 = 83,
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MX6UL_PAD_LCD_DATA14 = 84,
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MX6UL_PAD_LCD_DATA15 = 85,
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MX6UL_PAD_LCD_DATA16 = 86,
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MX6UL_PAD_LCD_DATA17 = 87,
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MX6UL_PAD_LCD_DATA18 = 88,
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MX6UL_PAD_LCD_DATA19 = 89,
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MX6UL_PAD_LCD_DATA20 = 90,
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MX6UL_PAD_LCD_DATA21 = 91,
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MX6UL_PAD_LCD_DATA22 = 92,
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MX6UL_PAD_LCD_DATA23 = 93,
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MX6UL_PAD_NAND_RE_B = 94,
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MX6UL_PAD_NAND_WE_B = 95,
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MX6UL_PAD_NAND_DATA00 = 96,
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MX6UL_PAD_NAND_DATA01 = 97,
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MX6UL_PAD_NAND_DATA02 = 98,
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MX6UL_PAD_NAND_DATA03 = 99,
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MX6UL_PAD_NAND_DATA04 = 100,
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MX6UL_PAD_NAND_DATA05 = 101,
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MX6UL_PAD_NAND_DATA06 = 102,
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MX6UL_PAD_NAND_DATA07 = 103,
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MX6UL_PAD_NAND_ALE = 104,
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MX6UL_PAD_NAND_WP_B = 105,
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MX6UL_PAD_NAND_READY_B = 106,
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MX6UL_PAD_NAND_CE0_B = 107,
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MX6UL_PAD_NAND_CE1_B = 108,
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MX6UL_PAD_NAND_CLE = 109,
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MX6UL_PAD_NAND_DQS = 110,
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MX6UL_PAD_SD1_CMD = 111,
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MX6UL_PAD_SD1_CLK = 112,
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MX6UL_PAD_SD1_DATA0 = 113,
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MX6UL_PAD_SD1_DATA1 = 114,
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MX6UL_PAD_SD1_DATA2 = 115,
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MX6UL_PAD_SD1_DATA3 = 116,
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MX6UL_PAD_CSI_MCLK = 117,
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MX6UL_PAD_CSI_PIXCLK = 118,
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MX6UL_PAD_CSI_VSYNC = 119,
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MX6UL_PAD_CSI_HSYNC = 120,
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MX6UL_PAD_CSI_DATA00 = 121,
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MX6UL_PAD_CSI_DATA01 = 122,
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MX6UL_PAD_CSI_DATA02 = 123,
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MX6UL_PAD_CSI_DATA03 = 124,
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MX6UL_PAD_CSI_DATA04 = 125,
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MX6UL_PAD_CSI_DATA05 = 126,
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MX6UL_PAD_CSI_DATA06 = 127,
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MX6UL_PAD_CSI_DATA07 = 128,
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};
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enum imx6ull_lpsr_pads {
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MX6ULL_PAD_BOOT_MODE0 = 0,
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MX6ULL_PAD_BOOT_MODE1 = 1,
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MX6ULL_PAD_SNVS_TAMPER0 = 2,
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MX6ULL_PAD_SNVS_TAMPER1 = 3,
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MX6ULL_PAD_SNVS_TAMPER2 = 4,
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MX6ULL_PAD_SNVS_TAMPER3 = 5,
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MX6ULL_PAD_SNVS_TAMPER4 = 6,
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MX6ULL_PAD_SNVS_TAMPER5 = 7,
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MX6ULL_PAD_SNVS_TAMPER6 = 8,
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MX6ULL_PAD_SNVS_TAMPER7 = 9,
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MX6ULL_PAD_SNVS_TAMPER8 = 10,
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MX6ULL_PAD_SNVS_TAMPER9 = 11,
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE1),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE2),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE3),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE4),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE5),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE6),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE7),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE8),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE9),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE10),
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IMX_PINCTRL_PIN(MX6UL_PAD_SNVS_TAMPER4),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE12),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE13),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE14),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE15),
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IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE16),
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IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_MOD),
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IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TMS),
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IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDO),
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IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDI),
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IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TCK),
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IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TRST_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO00),
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IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO01),
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IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO02),
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IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO03),
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IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO04),
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IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO05),
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IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO06),
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IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO07),
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IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO08),
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IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO09),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART1_TX_DATA),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RX_DATA),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART1_CTS_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RTS_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART2_TX_DATA),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RX_DATA),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART2_CTS_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RTS_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART3_TX_DATA),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RX_DATA),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART3_CTS_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RTS_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART4_TX_DATA),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART4_RX_DATA),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART5_TX_DATA),
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IMX_PINCTRL_PIN(MX6UL_PAD_UART5_RX_DATA),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA0),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA1),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_EN),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA0),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA1),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_EN),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_CLK),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_ER),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA0),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA1),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_EN),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA0),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA1),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_EN),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_CLK),
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IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_ER),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_CLK),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_ENABLE),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_HSYNC),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_VSYNC),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_RESET),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA00),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA01),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA02),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA03),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA04),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA05),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA06),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA07),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA08),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA09),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA10),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA11),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA12),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA13),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA14),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA15),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA16),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA17),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA18),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA19),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA20),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA21),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA22),
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IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA23),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_RE_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WE_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA00),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA01),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA02),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA03),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA04),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA05),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA06),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA07),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_ALE),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WP_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_READY_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE0_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE1_B),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CLE),
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IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DQS),
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IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CMD),
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IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CLK),
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IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA0),
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IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA1),
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IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA2),
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IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA3),
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IMX_PINCTRL_PIN(MX6UL_PAD_CSI_MCLK),
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IMX_PINCTRL_PIN(MX6UL_PAD_CSI_PIXCLK),
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IMX_PINCTRL_PIN(MX6UL_PAD_CSI_VSYNC),
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IMX_PINCTRL_PIN(MX6UL_PAD_CSI_HSYNC),
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IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA00),
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IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA01),
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IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA02),
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IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA03),
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IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA04),
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IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA05),
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IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA06),
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IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07),
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};
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/* pad for i.MX6ULL lpsr pinmux */
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static const struct pinctrl_pin_desc imx6ull_snvs_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE0),
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IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE1),
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IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER0),
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IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER1),
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IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER2),
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IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER3),
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IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER4),
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IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER5),
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IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER6),
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IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER7),
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IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER8),
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IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER9),
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};
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static const struct imx_pinctrl_soc_info imx6ul_pinctrl_info = {
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.pins = imx6ul_pinctrl_pads,
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.npins = ARRAY_SIZE(imx6ul_pinctrl_pads),
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.gpr_compatible = "fsl,imx6ul-iomuxc-gpr",
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};
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static const struct imx_pinctrl_soc_info imx6ull_snvs_pinctrl_info = {
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.pins = imx6ull_snvs_pinctrl_pads,
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.npins = ARRAY_SIZE(imx6ull_snvs_pinctrl_pads),
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.flags = ZERO_OFFSET_VALID,
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};
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static const struct of_device_id imx6ul_pinctrl_of_match[] = {
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{ .compatible = "fsl,imx6ul-iomuxc", .data = &imx6ul_pinctrl_info, },
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{ .compatible = "fsl,imx6ull-iomuxc-snvs", .data = &imx6ull_snvs_pinctrl_info, },
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{ /* sentinel */ }
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};
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static int imx6ul_pinctrl_probe(struct platform_device *pdev)
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{
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const struct imx_pinctrl_soc_info *pinctrl_info;
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pinctrl_info = of_device_get_match_data(&pdev->dev);
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if (!pinctrl_info)
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return -ENODEV;
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return imx_pinctrl_probe(pdev, pinctrl_info);
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}
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static struct platform_driver imx6ul_pinctrl_driver = {
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.driver = {
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.name = "imx6ul-pinctrl",
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.of_match_table = of_match_ptr(imx6ul_pinctrl_of_match),
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},
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.probe = imx6ul_pinctrl_probe,
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};
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static int __init imx6ul_pinctrl_init(void)
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{
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return platform_driver_register(&imx6ul_pinctrl_driver);
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}
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arch_initcall(imx6ul_pinctrl_init);
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