/*
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* ricoh.h 1.9 1999/10/25 20:03:34
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*
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* The contents of this file are subject to the Mozilla Public License
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* Version 1.1 (the "License"); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License
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* at http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS"
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* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
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* the License for the specific language governing rights and
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* limitations under the License.
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*
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* The initial developer of the original code is David A. Hinds
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* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
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* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
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*
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* Alternatively, the contents of this file may be used under the
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* terms of the GNU General Public License version 2 (the "GPL"), in which
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* case the provisions of the GPL are applicable instead of the
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* above. If you wish to allow the use of your version of this file
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* only under the terms of the GPL and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the GPL. If you do not delete the
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* provisions above, a recipient may use your version of this file
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* under either the MPL or the GPL.
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*/
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#ifndef _LINUX_RICOH_H
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#define _LINUX_RICOH_H
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#define RF5C_MODE_CTL 0x1f /* Mode control */
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#define RF5C_PWR_CTL 0x2f /* Mixed voltage control */
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#define RF5C_CHIP_ID 0x3a /* Chip identification */
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#define RF5C_MODE_CTL_3 0x3b /* Mode control 3 */
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/* I/O window address offset */
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#define RF5C_IO_OFF(w) (0x36+((w)<<1))
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/* Flags for RF5C_MODE_CTL */
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#define RF5C_MODE_ATA 0x01 /* ATA mode */
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#define RF5C_MODE_LED_ENA 0x02 /* IRQ 12 is LED */
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#define RF5C_MODE_CA21 0x04
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#define RF5C_MODE_CA22 0x08
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#define RF5C_MODE_CA23 0x10
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#define RF5C_MODE_CA24 0x20
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#define RF5C_MODE_CA25 0x40
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#define RF5C_MODE_3STATE_BIT7 0x80
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/* Flags for RF5C_PWR_CTL */
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#define RF5C_PWR_VCC_3V 0x01
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#define RF5C_PWR_IREQ_HIGH 0x02
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#define RF5C_PWR_INPACK_ENA 0x04
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#define RF5C_PWR_5V_DET 0x08
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#define RF5C_PWR_TC_SEL 0x10 /* Terminal Count: irq 11 or 15 */
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#define RF5C_PWR_DREQ_LOW 0x20
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#define RF5C_PWR_DREQ_OFF 0x00 /* DREQ steering control */
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#define RF5C_PWR_DREQ_INPACK 0x40
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#define RF5C_PWR_DREQ_SPKR 0x80
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#define RF5C_PWR_DREQ_IOIS16 0xc0
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/* Values for RF5C_CHIP_ID */
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#define RF5C_CHIP_RF5C296 0x32
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#define RF5C_CHIP_RF5C396 0xb2
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/* Flags for RF5C_MODE_CTL_3 */
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#define RF5C_MCTL3_DISABLE 0x01 /* Disable PCMCIA interface */
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#define RF5C_MCTL3_DMA_ENA 0x02
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/* Register definitions for Ricoh PCI-to-CardBus bridges */
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/* Extra bits in CB_BRIDGE_CONTROL */
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#define RL5C46X_BCR_3E0_ENA 0x0800
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#define RL5C46X_BCR_3E2_ENA 0x1000
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/* Bridge Configuration Register */
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#define RL5C4XX_CONFIG 0x80 /* 16 bit */
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#define RL5C4XX_CONFIG_IO_1_MODE 0x0200
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#define RL5C4XX_CONFIG_IO_0_MODE 0x0100
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#define RL5C4XX_CONFIG_PREFETCH 0x0001
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/* Misc Control Register */
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#define RL5C4XX_MISC 0x0082 /* 16 bit */
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#define RL5C4XX_MISC_HW_SUSPEND_ENA 0x0002
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#define RL5C4XX_MISC_VCCEN_POL 0x0100
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#define RL5C4XX_MISC_VPPEN_POL 0x0200
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#define RL5C46X_MISC_SUSPEND 0x0001
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#define RL5C46X_MISC_PWR_SAVE_2 0x0004
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#define RL5C46X_MISC_IFACE_BUSY 0x0008
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#define RL5C46X_MISC_B_LOCK 0x0010
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#define RL5C46X_MISC_A_LOCK 0x0020
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#define RL5C46X_MISC_PCI_LOCK 0x0040
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#define RL5C47X_MISC_IFACE_BUSY 0x0004
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#define RL5C47X_MISC_PCI_INT_MASK 0x0018
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#define RL5C47X_MISC_PCI_INT_DIS 0x0020
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#define RL5C47X_MISC_SUBSYS_WR 0x0040
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#define RL5C47X_MISC_SRIRQ_ENA 0x0080
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#define RL5C47X_MISC_5V_DISABLE 0x0400
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#define RL5C47X_MISC_LED_POL 0x0800
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/* 16-bit Interface Control Register */
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#define RL5C4XX_16BIT_CTL 0x0084 /* 16 bit */
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#define RL5C4XX_16CTL_IO_TIMING 0x0100
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#define RL5C4XX_16CTL_MEM_TIMING 0x0200
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#define RL5C46X_16CTL_LEVEL_1 0x0010
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#define RL5C46X_16CTL_LEVEL_2 0x0020
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/* 16-bit IO and memory timing registers */
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#define RL5C4XX_16BIT_IO_0 0x0088 /* 16 bit */
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#define RL5C4XX_16BIT_MEM_0 0x008a /* 16 bit */
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#define RL5C4XX_SETUP_MASK 0x0007
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#define RL5C4XX_SETUP_SHIFT 0
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#define RL5C4XX_CMD_MASK 0x01f0
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#define RL5C4XX_CMD_SHIFT 4
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#define RL5C4XX_HOLD_MASK 0x1c00
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#define RL5C4XX_HOLD_SHIFT 10
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#define RL5C4XX_MISC_CONTROL 0x2F /* 8 bit */
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#define RL5C4XX_ZV_ENABLE 0x08
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/* Misc Control 3 Register */
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#define RL5C4XX_MISC3 0x00A2 /* 16 bit */
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#define RL5C47X_MISC3_CB_CLKRUN_DIS BIT(1)
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#ifdef __YENTA_H
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#define rl_misc(socket) ((socket)->private[0])
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#define rl_ctl(socket) ((socket)->private[1])
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#define rl_io(socket) ((socket)->private[2])
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#define rl_mem(socket) ((socket)->private[3])
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#define rl_config(socket) ((socket)->private[4])
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static void ricoh_zoom_video(struct pcmcia_socket *sock, int onoff)
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{
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u8 reg;
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struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
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reg = config_readb(socket, RL5C4XX_MISC_CONTROL);
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if (onoff)
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/* Zoom zoom, we will all go together, zoom zoom, zoom zoom */
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reg |= RL5C4XX_ZV_ENABLE;
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else
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reg &= ~RL5C4XX_ZV_ENABLE;
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config_writeb(socket, RL5C4XX_MISC_CONTROL, reg);
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}
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static void ricoh_set_zv(struct yenta_socket *socket)
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{
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if(socket->dev->vendor == PCI_VENDOR_ID_RICOH)
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{
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switch(socket->dev->device)
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{
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/* There may be more .. */
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case PCI_DEVICE_ID_RICOH_RL5C478:
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socket->socket.zoom_video = ricoh_zoom_video;
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break;
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}
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}
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}
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static void ricoh_set_clkrun(struct yenta_socket *socket, bool quiet)
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{
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u16 misc3;
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/*
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* RL5C475II likely has this setting, too, however no datasheet
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* is publicly available for this chip
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*/
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if (socket->dev->device != PCI_DEVICE_ID_RICOH_RL5C476 &&
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socket->dev->device != PCI_DEVICE_ID_RICOH_RL5C478)
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return;
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if (socket->dev->revision < 0x80)
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return;
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misc3 = config_readw(socket, RL5C4XX_MISC3);
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if (misc3 & RL5C47X_MISC3_CB_CLKRUN_DIS) {
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if (!quiet)
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dev_dbg(&socket->dev->dev,
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"CLKRUN feature already disabled\n");
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} else if (disable_clkrun) {
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if (!quiet)
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dev_info(&socket->dev->dev,
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"Disabling CLKRUN feature\n");
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misc3 |= RL5C47X_MISC3_CB_CLKRUN_DIS;
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config_writew(socket, RL5C4XX_MISC3, misc3);
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}
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}
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static void ricoh_save_state(struct yenta_socket *socket)
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{
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rl_misc(socket) = config_readw(socket, RL5C4XX_MISC);
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rl_ctl(socket) = config_readw(socket, RL5C4XX_16BIT_CTL);
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rl_io(socket) = config_readw(socket, RL5C4XX_16BIT_IO_0);
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rl_mem(socket) = config_readw(socket, RL5C4XX_16BIT_MEM_0);
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rl_config(socket) = config_readw(socket, RL5C4XX_CONFIG);
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}
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static void ricoh_restore_state(struct yenta_socket *socket)
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{
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config_writew(socket, RL5C4XX_MISC, rl_misc(socket));
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config_writew(socket, RL5C4XX_16BIT_CTL, rl_ctl(socket));
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config_writew(socket, RL5C4XX_16BIT_IO_0, rl_io(socket));
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config_writew(socket, RL5C4XX_16BIT_MEM_0, rl_mem(socket));
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config_writew(socket, RL5C4XX_CONFIG, rl_config(socket));
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ricoh_set_clkrun(socket, true);
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}
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/*
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* Magic Ricoh initialization code..
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*/
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static int ricoh_override(struct yenta_socket *socket)
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{
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u16 config, ctl;
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config = config_readw(socket, RL5C4XX_CONFIG);
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/* Set the default timings, don't trust the original values */
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ctl = RL5C4XX_16CTL_IO_TIMING | RL5C4XX_16CTL_MEM_TIMING;
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if(socket->dev->device < PCI_DEVICE_ID_RICOH_RL5C475) {
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ctl |= RL5C46X_16CTL_LEVEL_1 | RL5C46X_16CTL_LEVEL_2;
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} else {
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config |= RL5C4XX_CONFIG_PREFETCH;
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}
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config_writew(socket, RL5C4XX_16BIT_CTL, ctl);
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config_writew(socket, RL5C4XX_CONFIG, config);
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ricoh_set_zv(socket);
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ricoh_set_clkrun(socket, false);
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return 0;
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}
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#endif /* CONFIG_CARDBUS */
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#endif /* _LINUX_RICOH_H */
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