/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2009 - 2018 Intel Corporation. */
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#ifndef _E1000_REGS_H_
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#define _E1000_REGS_H_
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#define E1000_CTRL 0x00000 /* Device Control - RW */
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#define E1000_STATUS 0x00008 /* Device Status - RO */
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#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
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#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
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#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
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#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
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#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
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#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
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#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
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#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
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#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
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#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
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/* Convenience macros
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*
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* Note: "_n" is the queue number of the register to be written to.
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*
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* Example usage:
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* E1000_RDBAL_REG(current_rx_queue)
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*/
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#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
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(0x0C000 + ((_n) * 0x40)))
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#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
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(0x0C004 + ((_n) * 0x40)))
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#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
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(0x0C008 + ((_n) * 0x40)))
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#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
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(0x0C00C + ((_n) * 0x40)))
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#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
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(0x0C010 + ((_n) * 0x40)))
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#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
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(0x0C018 + ((_n) * 0x40)))
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#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
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(0x0C028 + ((_n) * 0x40)))
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#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
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(0x0E000 + ((_n) * 0x40)))
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#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
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(0x0E004 + ((_n) * 0x40)))
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#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
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(0x0E008 + ((_n) * 0x40)))
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#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
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(0x0E010 + ((_n) * 0x40)))
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#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
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(0x0E018 + ((_n) * 0x40)))
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#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
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(0x0E028 + ((_n) * 0x40)))
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#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
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#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
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#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
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(0x054E0 + ((_i - 16) * 8)))
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#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
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(0x054E4 + ((_i - 16) * 8)))
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/* Statistics registers */
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#define E1000_VFGPRC 0x00F10
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#define E1000_VFGORC 0x00F18
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#define E1000_VFMPRC 0x00F3C
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#define E1000_VFGPTC 0x00F14
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#define E1000_VFGOTC 0x00F34
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#define E1000_VFGOTLBC 0x00F50
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#define E1000_VFGPTLBC 0x00F44
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#define E1000_VFGORLBC 0x00F48
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#define E1000_VFGPRLBC 0x00F40
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/* These act per VF so an array friendly macro is used */
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#define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n)))
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#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))
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/* Define macros for handling registers */
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#define er32(reg) readl(hw->hw_addr + E1000_##reg)
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#define ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg)
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#define array_er32(reg, offset) \
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readl(hw->hw_addr + E1000_##reg + (offset << 2))
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#define array_ew32(reg, offset, val) \
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writel((val), hw->hw_addr + E1000_##reg + (offset << 2))
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#define e1e_flush() er32(STATUS)
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#endif
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