// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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/*
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* Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
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*/
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#include "ena_eth_com.h"
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static struct ena_eth_io_rx_cdesc_base *ena_com_get_next_rx_cdesc(
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struct ena_com_io_cq *io_cq)
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{
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struct ena_eth_io_rx_cdesc_base *cdesc;
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u16 expected_phase, head_masked;
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u16 desc_phase;
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head_masked = io_cq->head & (io_cq->q_depth - 1);
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expected_phase = io_cq->phase;
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cdesc = (struct ena_eth_io_rx_cdesc_base *)(io_cq->cdesc_addr.virt_addr
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+ (head_masked * io_cq->cdesc_entry_size_in_bytes));
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desc_phase = (READ_ONCE(cdesc->status) &
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ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >>
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ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
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if (desc_phase != expected_phase)
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return NULL;
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/* Make sure we read the rest of the descriptor after the phase bit
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* has been read
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*/
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dma_rmb();
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return cdesc;
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}
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static void *get_sq_desc_regular_queue(struct ena_com_io_sq *io_sq)
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{
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u16 tail_masked;
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u32 offset;
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tail_masked = io_sq->tail & (io_sq->q_depth - 1);
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offset = tail_masked * io_sq->desc_entry_size;
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return (void *)((uintptr_t)io_sq->desc_addr.virt_addr + offset);
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}
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static int ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq *io_sq,
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u8 *bounce_buffer)
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{
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struct ena_com_llq_info *llq_info = &io_sq->llq_info;
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u16 dst_tail_mask;
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u32 dst_offset;
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dst_tail_mask = io_sq->tail & (io_sq->q_depth - 1);
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dst_offset = dst_tail_mask * llq_info->desc_list_entry_size;
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if (is_llq_max_tx_burst_exists(io_sq)) {
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if (unlikely(!io_sq->entries_in_tx_burst_left)) {
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pr_err("Error: trying to send more packets than tx burst allows\n");
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return -ENOSPC;
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}
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io_sq->entries_in_tx_burst_left--;
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pr_debug("Decreasing entries_in_tx_burst_left of queue %d to %d\n",
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io_sq->qid, io_sq->entries_in_tx_burst_left);
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}
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/* Make sure everything was written into the bounce buffer before
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* writing the bounce buffer to the device
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*/
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wmb();
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/* The line is completed. Copy it to dev */
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__iowrite64_copy(io_sq->desc_addr.pbuf_dev_addr + dst_offset,
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bounce_buffer, (llq_info->desc_list_entry_size) / 8);
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io_sq->tail++;
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/* Switch phase bit in case of wrap around */
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if (unlikely((io_sq->tail & (io_sq->q_depth - 1)) == 0))
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io_sq->phase ^= 1;
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return 0;
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}
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static int ena_com_write_header_to_bounce(struct ena_com_io_sq *io_sq,
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u8 *header_src,
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u16 header_len)
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{
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struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
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struct ena_com_llq_info *llq_info = &io_sq->llq_info;
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u8 *bounce_buffer = pkt_ctrl->curr_bounce_buf;
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u16 header_offset;
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if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST))
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return 0;
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header_offset =
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llq_info->descs_num_before_header * io_sq->desc_entry_size;
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if (unlikely((header_offset + header_len) >
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llq_info->desc_list_entry_size)) {
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pr_err("Trying to write header larger than llq entry can accommodate\n");
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return -EFAULT;
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}
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if (unlikely(!bounce_buffer)) {
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pr_err("Bounce buffer is NULL\n");
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return -EFAULT;
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}
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memcpy(bounce_buffer + header_offset, header_src, header_len);
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return 0;
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}
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static void *get_sq_desc_llq(struct ena_com_io_sq *io_sq)
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{
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struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
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u8 *bounce_buffer;
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void *sq_desc;
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bounce_buffer = pkt_ctrl->curr_bounce_buf;
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if (unlikely(!bounce_buffer)) {
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pr_err("Bounce buffer is NULL\n");
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return NULL;
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}
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sq_desc = bounce_buffer + pkt_ctrl->idx * io_sq->desc_entry_size;
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pkt_ctrl->idx++;
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pkt_ctrl->descs_left_in_line--;
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return sq_desc;
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}
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static int ena_com_close_bounce_buffer(struct ena_com_io_sq *io_sq)
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{
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struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
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struct ena_com_llq_info *llq_info = &io_sq->llq_info;
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int rc;
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if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST))
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return 0;
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/* bounce buffer was used, so write it and get a new one */
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if (pkt_ctrl->idx) {
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rc = ena_com_write_bounce_buffer_to_dev(io_sq,
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pkt_ctrl->curr_bounce_buf);
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if (unlikely(rc))
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return rc;
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pkt_ctrl->curr_bounce_buf =
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ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
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memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
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0x0, llq_info->desc_list_entry_size);
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}
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pkt_ctrl->idx = 0;
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pkt_ctrl->descs_left_in_line = llq_info->descs_num_before_header;
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return 0;
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}
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static void *get_sq_desc(struct ena_com_io_sq *io_sq)
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{
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if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
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return get_sq_desc_llq(io_sq);
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return get_sq_desc_regular_queue(io_sq);
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}
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static int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq)
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{
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struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
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struct ena_com_llq_info *llq_info = &io_sq->llq_info;
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int rc;
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if (!pkt_ctrl->descs_left_in_line) {
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rc = ena_com_write_bounce_buffer_to_dev(io_sq,
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pkt_ctrl->curr_bounce_buf);
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if (unlikely(rc))
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return rc;
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pkt_ctrl->curr_bounce_buf =
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ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
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memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
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0x0, llq_info->desc_list_entry_size);
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pkt_ctrl->idx = 0;
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if (unlikely(llq_info->desc_stride_ctrl == ENA_ADMIN_SINGLE_DESC_PER_ENTRY))
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pkt_ctrl->descs_left_in_line = 1;
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else
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pkt_ctrl->descs_left_in_line =
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llq_info->desc_list_entry_size / io_sq->desc_entry_size;
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}
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return 0;
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}
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static int ena_com_sq_update_tail(struct ena_com_io_sq *io_sq)
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{
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if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
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return ena_com_sq_update_llq_tail(io_sq);
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io_sq->tail++;
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/* Switch phase bit in case of wrap around */
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if (unlikely((io_sq->tail & (io_sq->q_depth - 1)) == 0))
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io_sq->phase ^= 1;
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return 0;
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}
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static struct ena_eth_io_rx_cdesc_base *
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ena_com_rx_cdesc_idx_to_ptr(struct ena_com_io_cq *io_cq, u16 idx)
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{
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idx &= (io_cq->q_depth - 1);
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return (struct ena_eth_io_rx_cdesc_base *)
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((uintptr_t)io_cq->cdesc_addr.virt_addr +
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idx * io_cq->cdesc_entry_size_in_bytes);
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}
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static u16 ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
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u16 *first_cdesc_idx)
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{
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struct ena_eth_io_rx_cdesc_base *cdesc;
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u16 count = 0, head_masked;
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u32 last = 0;
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do {
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cdesc = ena_com_get_next_rx_cdesc(io_cq);
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if (!cdesc)
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break;
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ena_com_cq_inc_head(io_cq);
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count++;
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last = (READ_ONCE(cdesc->status) &
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ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >>
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ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;
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} while (!last);
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if (last) {
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*first_cdesc_idx = io_cq->cur_rx_pkt_cdesc_start_idx;
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count += io_cq->cur_rx_pkt_cdesc_count;
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head_masked = io_cq->head & (io_cq->q_depth - 1);
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io_cq->cur_rx_pkt_cdesc_count = 0;
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io_cq->cur_rx_pkt_cdesc_start_idx = head_masked;
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pr_debug("ENA q_id: %d packets were completed. first desc idx %u descs# %d\n",
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io_cq->qid, *first_cdesc_idx, count);
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} else {
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io_cq->cur_rx_pkt_cdesc_count += count;
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count = 0;
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}
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return count;
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}
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static int ena_com_create_meta(struct ena_com_io_sq *io_sq,
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struct ena_com_tx_meta *ena_meta)
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{
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struct ena_eth_io_tx_meta_desc *meta_desc = NULL;
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meta_desc = get_sq_desc(io_sq);
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if (unlikely(!meta_desc))
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return -EFAULT;
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memset(meta_desc, 0x0, sizeof(struct ena_eth_io_tx_meta_desc));
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meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;
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meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
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/* bits 0-9 of the mss */
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meta_desc->word2 |= ((u32)ena_meta->mss <<
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ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) &
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ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
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/* bits 10-13 of the mss */
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meta_desc->len_ctrl |= ((ena_meta->mss >> 10) <<
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ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) &
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ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK;
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/* Extended meta desc */
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meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
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meta_desc->len_ctrl |= ((u32)io_sq->phase <<
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ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) &
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ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
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meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_FIRST_MASK;
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meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;
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meta_desc->word2 |= ena_meta->l3_hdr_len &
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ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
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meta_desc->word2 |= (ena_meta->l3_hdr_offset <<
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ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) &
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ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;
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meta_desc->word2 |= ((u32)ena_meta->l4_hdr_len <<
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ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) &
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ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;
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return ena_com_sq_update_tail(io_sq);
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}
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static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq,
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struct ena_com_tx_ctx *ena_tx_ctx,
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bool *have_meta)
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{
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struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
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/* When disable meta caching is set, don't bother to save the meta and
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* compare it to the stored version, just create the meta
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*/
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if (io_sq->disable_meta_caching) {
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if (unlikely(!ena_tx_ctx->meta_valid))
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return -EINVAL;
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*have_meta = true;
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return ena_com_create_meta(io_sq, ena_meta);
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}
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if (ena_com_meta_desc_changed(io_sq, ena_tx_ctx)) {
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*have_meta = true;
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/* Cache the meta desc */
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memcpy(&io_sq->cached_tx_meta, ena_meta,
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sizeof(struct ena_com_tx_meta));
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return ena_com_create_meta(io_sq, ena_meta);
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}
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*have_meta = false;
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return 0;
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}
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static void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx,
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struct ena_eth_io_rx_cdesc_base *cdesc)
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{
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ena_rx_ctx->l3_proto = cdesc->status &
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ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
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ena_rx_ctx->l4_proto =
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(cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >>
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ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;
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ena_rx_ctx->l3_csum_err =
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!!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >>
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ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT);
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ena_rx_ctx->l4_csum_err =
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!!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >>
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ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT);
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ena_rx_ctx->l4_csum_checked =
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!!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >>
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ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT);
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ena_rx_ctx->hash = cdesc->hash;
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ena_rx_ctx->frag =
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(cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >>
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ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
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pr_debug("l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %d frag %d cdesc_status %x\n",
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ena_rx_ctx->l3_proto, ena_rx_ctx->l4_proto,
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ena_rx_ctx->l3_csum_err, ena_rx_ctx->l4_csum_err,
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ena_rx_ctx->hash, ena_rx_ctx->frag, cdesc->status);
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}
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/*****************************************************************************/
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/***************************** API **********************************/
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/*****************************************************************************/
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int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
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struct ena_com_tx_ctx *ena_tx_ctx,
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int *nb_hw_desc)
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{
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struct ena_eth_io_tx_desc *desc = NULL;
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struct ena_com_buf *ena_bufs = ena_tx_ctx->ena_bufs;
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void *buffer_to_push = ena_tx_ctx->push_header;
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u16 header_len = ena_tx_ctx->header_len;
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u16 num_bufs = ena_tx_ctx->num_bufs;
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u16 start_tail = io_sq->tail;
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int i, rc;
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bool have_meta;
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u64 addr_hi;
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WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_TX, "wrong Q type");
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/* num_bufs +1 for potential meta desc */
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if (unlikely(!ena_com_sq_have_enough_space(io_sq, num_bufs + 1))) {
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pr_debug("Not enough space in the tx queue\n");
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return -ENOMEM;
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}
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if (unlikely(header_len > io_sq->tx_max_header_size)) {
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pr_err("Header size is too large %d max header: %d\n",
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header_len, io_sq->tx_max_header_size);
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return -EINVAL;
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}
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if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
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!buffer_to_push))
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return -EINVAL;
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rc = ena_com_write_header_to_bounce(io_sq, buffer_to_push, header_len);
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if (unlikely(rc))
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return rc;
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rc = ena_com_create_and_store_tx_meta_desc(io_sq, ena_tx_ctx, &have_meta);
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if (unlikely(rc)) {
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pr_err("Failed to create and store tx meta desc\n");
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return rc;
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}
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/* If the caller doesn't want to send packets */
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if (unlikely(!num_bufs && !header_len)) {
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rc = ena_com_close_bounce_buffer(io_sq);
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*nb_hw_desc = io_sq->tail - start_tail;
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return rc;
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}
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desc = get_sq_desc(io_sq);
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if (unlikely(!desc))
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return -EFAULT;
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memset(desc, 0x0, sizeof(struct ena_eth_io_tx_desc));
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/* Set first desc when we don't have meta descriptor */
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if (!have_meta)
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desc->len_ctrl |= ENA_ETH_IO_TX_DESC_FIRST_MASK;
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desc->buff_addr_hi_hdr_sz |= ((u32)header_len <<
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ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) &
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ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;
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desc->len_ctrl |= ((u32)io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
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ENA_ETH_IO_TX_DESC_PHASE_MASK;
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desc->len_ctrl |= ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;
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/* Bits 0-9 */
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desc->meta_ctrl |= ((u32)ena_tx_ctx->req_id <<
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ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) &
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ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
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desc->meta_ctrl |= (ena_tx_ctx->df <<
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ENA_ETH_IO_TX_DESC_DF_SHIFT) &
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ENA_ETH_IO_TX_DESC_DF_MASK;
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/* Bits 10-15 */
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desc->len_ctrl |= ((ena_tx_ctx->req_id >> 10) <<
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ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) &
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ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK;
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if (ena_tx_ctx->meta_valid) {
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desc->meta_ctrl |= (ena_tx_ctx->tso_enable <<
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ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) &
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ENA_ETH_IO_TX_DESC_TSO_EN_MASK;
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desc->meta_ctrl |= ena_tx_ctx->l3_proto &
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ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
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desc->meta_ctrl |= (ena_tx_ctx->l4_proto <<
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ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) &
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ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK;
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desc->meta_ctrl |= (ena_tx_ctx->l3_csum_enable <<
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ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) &
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ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK;
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desc->meta_ctrl |= (ena_tx_ctx->l4_csum_enable <<
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ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) &
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ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK;
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desc->meta_ctrl |= (ena_tx_ctx->l4_csum_partial <<
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ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) &
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ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;
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}
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for (i = 0; i < num_bufs; i++) {
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/* The first desc share the same desc as the header */
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if (likely(i != 0)) {
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rc = ena_com_sq_update_tail(io_sq);
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if (unlikely(rc))
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return rc;
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desc = get_sq_desc(io_sq);
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if (unlikely(!desc))
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return -EFAULT;
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memset(desc, 0x0, sizeof(struct ena_eth_io_tx_desc));
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desc->len_ctrl |= ((u32)io_sq->phase <<
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ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
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ENA_ETH_IO_TX_DESC_PHASE_MASK;
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}
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desc->len_ctrl |= ena_bufs->len &
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ENA_ETH_IO_TX_DESC_LENGTH_MASK;
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addr_hi = ((ena_bufs->paddr &
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GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);
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desc->buff_addr_lo = (u32)ena_bufs->paddr;
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desc->buff_addr_hi_hdr_sz |= addr_hi &
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ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
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ena_bufs++;
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}
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/* set the last desc indicator */
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desc->len_ctrl |= ENA_ETH_IO_TX_DESC_LAST_MASK;
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rc = ena_com_sq_update_tail(io_sq);
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if (unlikely(rc))
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return rc;
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rc = ena_com_close_bounce_buffer(io_sq);
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*nb_hw_desc = io_sq->tail - start_tail;
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return rc;
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}
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int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
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struct ena_com_io_sq *io_sq,
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struct ena_com_rx_ctx *ena_rx_ctx)
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{
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struct ena_com_rx_buf_info *ena_buf = &ena_rx_ctx->ena_bufs[0];
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struct ena_eth_io_rx_cdesc_base *cdesc = NULL;
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u16 q_depth = io_cq->q_depth;
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u16 cdesc_idx = 0;
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u16 nb_hw_desc;
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u16 i = 0;
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WARN(io_cq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX, "wrong Q type");
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nb_hw_desc = ena_com_cdesc_rx_pkt_get(io_cq, &cdesc_idx);
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if (nb_hw_desc == 0) {
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ena_rx_ctx->descs = nb_hw_desc;
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return 0;
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}
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pr_debug("Fetch rx packet: queue %d completed desc: %d\n", io_cq->qid,
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nb_hw_desc);
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if (unlikely(nb_hw_desc > ena_rx_ctx->max_bufs)) {
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pr_err("Too many RX cdescs (%d) > MAX(%d)\n", nb_hw_desc,
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ena_rx_ctx->max_bufs);
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return -ENOSPC;
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}
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cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx);
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ena_rx_ctx->pkt_offset = cdesc->offset;
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do {
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ena_buf[i].len = cdesc->length;
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ena_buf[i].req_id = cdesc->req_id;
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if (unlikely(ena_buf[i].req_id >= q_depth))
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return -EIO;
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if (++i >= nb_hw_desc)
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break;
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cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx + i);
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} while (1);
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/* Update SQ head ptr */
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io_sq->next_to_comp += nb_hw_desc;
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pr_debug("[%s][QID#%d] Updating SQ head to: %d\n", __func__, io_sq->qid,
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io_sq->next_to_comp);
|
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/* Get rx flags from the last pkt */
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ena_com_rx_set_flags(ena_rx_ctx, cdesc);
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ena_rx_ctx->descs = nb_hw_desc;
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return 0;
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}
|
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int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
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struct ena_com_buf *ena_buf,
|
u16 req_id)
|
{
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struct ena_eth_io_rx_desc *desc;
|
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WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX, "wrong Q type");
|
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if (unlikely(!ena_com_sq_have_enough_space(io_sq, 1)))
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return -ENOSPC;
|
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desc = get_sq_desc(io_sq);
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if (unlikely(!desc))
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return -EFAULT;
|
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memset(desc, 0x0, sizeof(struct ena_eth_io_rx_desc));
|
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desc->length = ena_buf->len;
|
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desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK |
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ENA_ETH_IO_RX_DESC_LAST_MASK |
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(io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK) |
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ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
|
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desc->req_id = req_id;
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desc->buff_addr_lo = (u32)ena_buf->paddr;
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desc->buff_addr_hi =
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((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);
|
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return ena_com_sq_update_tail(io_sq);
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}
|
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bool ena_com_cq_empty(struct ena_com_io_cq *io_cq)
|
{
|
struct ena_eth_io_rx_cdesc_base *cdesc;
|
|
cdesc = ena_com_get_next_rx_cdesc(io_cq);
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if (cdesc)
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return false;
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else
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return true;
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}
|
