/*
|
* Copyright (c) 2003-2015 Broadcom Corporation
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
|
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/i2c.h>
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#include <linux/i2c-smbus.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#define XLP9XX_I2C_DIV 0x0
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#define XLP9XX_I2C_CTRL 0x1
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#define XLP9XX_I2C_CMD 0x2
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#define XLP9XX_I2C_STATUS 0x3
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#define XLP9XX_I2C_MTXFIFO 0x4
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#define XLP9XX_I2C_MRXFIFO 0x5
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#define XLP9XX_I2C_MFIFOCTRL 0x6
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#define XLP9XX_I2C_STXFIFO 0x7
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#define XLP9XX_I2C_SRXFIFO 0x8
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#define XLP9XX_I2C_SFIFOCTRL 0x9
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#define XLP9XX_I2C_SLAVEADDR 0xA
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#define XLP9XX_I2C_OWNADDR 0xB
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#define XLP9XX_I2C_FIFOWCNT 0xC
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#define XLP9XX_I2C_INTEN 0xD
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#define XLP9XX_I2C_INTST 0xE
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#define XLP9XX_I2C_WAITCNT 0xF
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#define XLP9XX_I2C_TIMEOUT 0X10
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#define XLP9XX_I2C_GENCALLADDR 0x11
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|
#define XLP9XX_I2C_STATUS_BUSY BIT(0)
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|
#define XLP9XX_I2C_CMD_START BIT(7)
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#define XLP9XX_I2C_CMD_STOP BIT(6)
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#define XLP9XX_I2C_CMD_READ BIT(5)
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#define XLP9XX_I2C_CMD_WRITE BIT(4)
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#define XLP9XX_I2C_CMD_ACK BIT(3)
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|
#define XLP9XX_I2C_CTRL_MCTLEN_SHIFT 16
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#define XLP9XX_I2C_CTRL_MCTLEN_MASK 0xffff0000
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#define XLP9XX_I2C_CTRL_RST BIT(8)
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#define XLP9XX_I2C_CTRL_EN BIT(6)
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#define XLP9XX_I2C_CTRL_MASTER BIT(4)
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#define XLP9XX_I2C_CTRL_FIFORD BIT(1)
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#define XLP9XX_I2C_CTRL_ADDMODE BIT(0)
|
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#define XLP9XX_I2C_INTEN_NACKADDR BIT(25)
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#define XLP9XX_I2C_INTEN_SADDR BIT(13)
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#define XLP9XX_I2C_INTEN_DATADONE BIT(12)
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#define XLP9XX_I2C_INTEN_ARLOST BIT(11)
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#define XLP9XX_I2C_INTEN_MFIFOFULL BIT(4)
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#define XLP9XX_I2C_INTEN_MFIFOEMTY BIT(3)
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#define XLP9XX_I2C_INTEN_MFIFOHI BIT(2)
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#define XLP9XX_I2C_INTEN_BUSERR BIT(0)
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#define XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT 8
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#define XLP9XX_I2C_MFIFOCTRL_LOTH_SHIFT 0
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#define XLP9XX_I2C_MFIFOCTRL_RST BIT(16)
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#define XLP9XX_I2C_SLAVEADDR_RW BIT(0)
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#define XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT 1
|
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#define XLP9XX_I2C_IP_CLK_FREQ 133000000UL
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#define XLP9XX_I2C_FIFO_SIZE 0x80U
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#define XLP9XX_I2C_TIMEOUT_MS 1000
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#define XLP9XX_I2C_BUSY_TIMEOUT 50
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#define XLP9XX_I2C_FIFO_WCNT_MASK 0xff
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#define XLP9XX_I2C_STATUS_ERRMASK (XLP9XX_I2C_INTEN_ARLOST | \
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XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_BUSERR)
|
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struct xlp9xx_i2c_dev {
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struct device *dev;
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struct i2c_adapter adapter;
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struct completion msg_complete;
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struct i2c_smbus_alert_setup alert_data;
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struct i2c_client *ara;
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int irq;
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bool msg_read;
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bool len_recv;
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bool client_pec;
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u32 __iomem *base;
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u32 msg_buf_remaining;
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u32 msg_len;
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u32 ip_clk_hz;
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u32 clk_hz;
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u32 msg_err;
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u8 *msg_buf;
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};
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static inline void xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev *priv,
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unsigned long reg, u32 val)
|
{
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writel(val, priv->base + reg);
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}
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static inline u32 xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev *priv,
|
unsigned long reg)
|
{
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return readl(priv->base + reg);
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}
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static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
|
{
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u32 inten;
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inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask;
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
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}
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static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
|
{
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u32 inten;
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|
inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) | mask;
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
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}
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static void xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev *priv)
|
{
|
u32 thres;
|
|
if (priv->len_recv)
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/* interrupt after the first read to examine
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* the length byte before proceeding further
|
*/
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thres = 1;
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else if (priv->msg_buf_remaining > XLP9XX_I2C_FIFO_SIZE)
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thres = XLP9XX_I2C_FIFO_SIZE;
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else
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thres = priv->msg_buf_remaining;
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
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thres << XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT);
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}
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static void xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev *priv)
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{
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u32 len, i;
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u8 *buf = priv->msg_buf;
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len = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE);
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for (i = 0; i < len; i++)
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MTXFIFO, buf[i]);
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priv->msg_buf_remaining -= len;
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priv->msg_buf += len;
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}
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static void xlp9xx_i2c_update_rlen(struct xlp9xx_i2c_dev *priv)
|
{
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u32 val, len;
|
|
/*
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* Update receive length. Re-read len to get the latest value,
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* and then add 4 to have a minimum value that can be safely
|
* written. This is to account for the byte read above, the
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* transfer in progress and any delays in the register I/O
|
*/
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val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
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len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
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XLP9XX_I2C_FIFO_WCNT_MASK;
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len = max_t(u32, priv->msg_len, len + 4);
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if (len >= I2C_SMBUS_BLOCK_MAX + 2)
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return;
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val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) |
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(len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
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}
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static void xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev *priv)
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{
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u32 len, i;
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u8 rlen, *buf = priv->msg_buf;
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len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
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XLP9XX_I2C_FIFO_WCNT_MASK;
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if (!len)
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return;
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if (priv->len_recv) {
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/* read length byte */
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rlen = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);
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/*
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* We expect at least 2 interrupts for I2C_M_RECV_LEN
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* transactions. The length is updated during the first
|
* interrupt, and the buffer contents are only copied
|
* during subsequent interrupts. If in case the interrupts
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* get merged we would complete the transaction without
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* copying out the bytes from RX fifo. To avoid this now we
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* drain the fifo as and when data is available.
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* We drained the rlen byte already, decrement total length
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* by one.
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*/
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len--;
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if (rlen > I2C_SMBUS_BLOCK_MAX || rlen == 0) {
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rlen = 0; /*abort transfer */
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priv->msg_buf_remaining = 0;
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priv->msg_len = 0;
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xlp9xx_i2c_update_rlen(priv);
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return;
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}
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*buf++ = rlen;
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if (priv->client_pec)
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++rlen; /* account for error check byte */
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/* update remaining bytes and message length */
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priv->msg_buf_remaining = rlen;
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priv->msg_len = rlen + 1;
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xlp9xx_i2c_update_rlen(priv);
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priv->len_recv = false;
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}
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len = min(priv->msg_buf_remaining, len);
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for (i = 0; i < len; i++, buf++)
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*buf = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);
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priv->msg_buf_remaining -= len;
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priv->msg_buf = buf;
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if (priv->msg_buf_remaining)
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xlp9xx_i2c_update_rx_fifo_thres(priv);
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}
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static irqreturn_t xlp9xx_i2c_isr(int irq, void *dev_id)
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{
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struct xlp9xx_i2c_dev *priv = dev_id;
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u32 status;
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status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTST);
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if (status == 0)
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return IRQ_NONE;
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTST, status);
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if (status & XLP9XX_I2C_STATUS_ERRMASK) {
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priv->msg_err = status;
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goto xfer_done;
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}
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/* SADDR ACK for SMBUS_QUICK */
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if ((status & XLP9XX_I2C_INTEN_SADDR) && (priv->msg_len == 0))
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goto xfer_done;
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if (!priv->msg_read) {
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if (status & XLP9XX_I2C_INTEN_MFIFOEMTY) {
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/* TX FIFO got empty, fill it up again */
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if (priv->msg_buf_remaining)
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xlp9xx_i2c_fill_tx_fifo(priv);
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else
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xlp9xx_i2c_mask_irq(priv,
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XLP9XX_I2C_INTEN_MFIFOEMTY);
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}
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} else {
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if (status & (XLP9XX_I2C_INTEN_DATADONE |
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XLP9XX_I2C_INTEN_MFIFOHI)) {
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/* data is in FIFO, read it */
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if (priv->msg_buf_remaining)
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xlp9xx_i2c_drain_rx_fifo(priv);
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}
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}
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/* Transfer complete */
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if (status & XLP9XX_I2C_INTEN_DATADONE)
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goto xfer_done;
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return IRQ_HANDLED;
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xfer_done:
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
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complete(&priv->msg_complete);
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return IRQ_HANDLED;
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}
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static int xlp9xx_i2c_check_bus_status(struct xlp9xx_i2c_dev *priv)
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{
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u32 status;
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u32 busy_timeout = XLP9XX_I2C_BUSY_TIMEOUT;
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while (busy_timeout) {
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status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_STATUS);
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if ((status & XLP9XX_I2C_STATUS_BUSY) == 0)
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break;
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busy_timeout--;
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usleep_range(1000, 1100);
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}
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if (!busy_timeout)
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return -EIO;
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return 0;
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}
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static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv)
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{
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u32 prescale;
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/*
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* The controller uses 5 * SCL clock internally.
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* So prescale value should be divided by 5.
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*/
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prescale = DIV_ROUND_UP(priv->ip_clk_hz, priv->clk_hz);
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prescale = ((prescale - 8) / 5) - 1;
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST);
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN |
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XLP9XX_I2C_CTRL_MASTER);
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_DIV, prescale);
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
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return 0;
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}
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static int xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev *priv, struct i2c_msg *msg,
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int last_msg)
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{
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unsigned long timeleft;
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u32 intr_mask, cmd, val, len;
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priv->msg_buf = msg->buf;
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priv->msg_buf_remaining = priv->msg_len = msg->len;
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priv->msg_err = 0;
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priv->msg_read = (msg->flags & I2C_M_RD);
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reinit_completion(&priv->msg_complete);
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/* Reset FIFO */
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
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XLP9XX_I2C_MFIFOCTRL_RST);
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/* set slave addr */
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_SLAVEADDR,
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(msg->addr << XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT) |
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(priv->msg_read ? XLP9XX_I2C_SLAVEADDR_RW : 0));
|
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/* Build control word for transfer */
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val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
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if (!priv->msg_read)
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val &= ~XLP9XX_I2C_CTRL_FIFORD;
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else
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val |= XLP9XX_I2C_CTRL_FIFORD; /* read */
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if (msg->flags & I2C_M_TEN)
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val |= XLP9XX_I2C_CTRL_ADDMODE; /* 10-bit address mode*/
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else
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val &= ~XLP9XX_I2C_CTRL_ADDMODE;
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priv->len_recv = msg->flags & I2C_M_RECV_LEN;
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len = priv->len_recv ? I2C_SMBUS_BLOCK_MAX + 2 : msg->len;
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priv->client_pec = msg->flags & I2C_CLIENT_PEC;
|
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/* set FIFO threshold if reading */
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if (priv->msg_read)
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xlp9xx_i2c_update_rx_fifo_thres(priv);
|
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/* set data length to be transferred */
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val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) |
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(len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
|
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/* fill fifo during tx */
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if (!priv->msg_read)
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xlp9xx_i2c_fill_tx_fifo(priv);
|
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/* set interrupt mask */
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intr_mask = (XLP9XX_I2C_INTEN_ARLOST | XLP9XX_I2C_INTEN_BUSERR |
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XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_DATADONE);
|
|
if (priv->msg_read) {
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intr_mask |= XLP9XX_I2C_INTEN_MFIFOHI;
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if (msg->len == 0)
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intr_mask |= XLP9XX_I2C_INTEN_SADDR;
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} else {
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if (msg->len == 0)
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intr_mask |= XLP9XX_I2C_INTEN_SADDR;
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else
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intr_mask |= XLP9XX_I2C_INTEN_MFIFOEMTY;
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}
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xlp9xx_i2c_unmask_irq(priv, intr_mask);
|
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/* set cmd reg */
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cmd = XLP9XX_I2C_CMD_START;
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if (msg->len)
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cmd |= (priv->msg_read ?
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XLP9XX_I2C_CMD_READ : XLP9XX_I2C_CMD_WRITE);
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if (last_msg)
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cmd |= XLP9XX_I2C_CMD_STOP;
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, cmd);
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timeleft = msecs_to_jiffies(XLP9XX_I2C_TIMEOUT_MS);
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timeleft = wait_for_completion_timeout(&priv->msg_complete, timeleft);
|
|
if (priv->msg_err & XLP9XX_I2C_INTEN_BUSERR) {
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dev_dbg(priv->dev, "transfer error %x!\n", priv->msg_err);
|
xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, XLP9XX_I2C_CMD_STOP);
|
return -EIO;
|
} else if (priv->msg_err & XLP9XX_I2C_INTEN_NACKADDR) {
|
return -ENXIO;
|
}
|
|
if (timeleft == 0) {
|
dev_dbg(priv->dev, "i2c transfer timed out!\n");
|
xlp9xx_i2c_init(priv);
|
return -ETIMEDOUT;
|
}
|
|
/* update msg->len with actual received length */
|
if (msg->flags & I2C_M_RECV_LEN) {
|
if (!priv->msg_len)
|
return -EPROTO;
|
msg->len = priv->msg_len;
|
}
|
return 0;
|
}
|
|
static int xlp9xx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
|
int num)
|
{
|
int i, ret;
|
struct xlp9xx_i2c_dev *priv = i2c_get_adapdata(adap);
|
|
ret = xlp9xx_i2c_check_bus_status(priv);
|
if (ret) {
|
xlp9xx_i2c_init(priv);
|
ret = xlp9xx_i2c_check_bus_status(priv);
|
if (ret)
|
return ret;
|
}
|
|
for (i = 0; i < num; i++) {
|
ret = xlp9xx_i2c_xfer_msg(priv, &msgs[i], i == num - 1);
|
if (ret != 0)
|
return ret;
|
}
|
|
return num;
|
}
|
|
static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter)
|
{
|
return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_READ_BLOCK_DATA |
|
I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
|
}
|
|
static const struct i2c_algorithm xlp9xx_i2c_algo = {
|
.master_xfer = xlp9xx_i2c_xfer,
|
.functionality = xlp9xx_i2c_functionality,
|
};
|
|
static int xlp9xx_i2c_get_frequency(struct platform_device *pdev,
|
struct xlp9xx_i2c_dev *priv)
|
{
|
struct clk *clk;
|
u32 freq;
|
int err;
|
|
clk = devm_clk_get(&pdev->dev, NULL);
|
if (IS_ERR(clk)) {
|
priv->ip_clk_hz = XLP9XX_I2C_IP_CLK_FREQ;
|
dev_dbg(&pdev->dev, "using default input frequency %u\n",
|
priv->ip_clk_hz);
|
} else {
|
priv->ip_clk_hz = clk_get_rate(clk);
|
}
|
|
err = device_property_read_u32(&pdev->dev, "clock-frequency", &freq);
|
if (err) {
|
freq = I2C_MAX_STANDARD_MODE_FREQ;
|
dev_dbg(&pdev->dev, "using default frequency %u\n", freq);
|
} else if (freq == 0 || freq > I2C_MAX_FAST_MODE_FREQ) {
|
dev_warn(&pdev->dev, "invalid frequency %u, using default\n",
|
freq);
|
freq = I2C_MAX_STANDARD_MODE_FREQ;
|
}
|
priv->clk_hz = freq;
|
|
return 0;
|
}
|
|
static int xlp9xx_i2c_smbus_setup(struct xlp9xx_i2c_dev *priv,
|
struct platform_device *pdev)
|
{
|
struct i2c_client *ara;
|
|
if (!priv->alert_data.irq)
|
return -EINVAL;
|
|
ara = i2c_new_smbus_alert_device(&priv->adapter, &priv->alert_data);
|
if (IS_ERR(ara))
|
return PTR_ERR(ara);
|
|
priv->ara = ara;
|
|
return 0;
|
}
|
|
static int xlp9xx_i2c_probe(struct platform_device *pdev)
|
{
|
struct xlp9xx_i2c_dev *priv;
|
int err = 0;
|
|
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
if (!priv)
|
return -ENOMEM;
|
|
priv->base = devm_platform_ioremap_resource(pdev, 0);
|
if (IS_ERR(priv->base))
|
return PTR_ERR(priv->base);
|
|
priv->irq = platform_get_irq(pdev, 0);
|
if (priv->irq < 0)
|
return priv->irq;
|
/* SMBAlert irq */
|
priv->alert_data.irq = platform_get_irq(pdev, 1);
|
if (priv->alert_data.irq <= 0)
|
priv->alert_data.irq = 0;
|
|
xlp9xx_i2c_get_frequency(pdev, priv);
|
xlp9xx_i2c_init(priv);
|
|
err = devm_request_irq(&pdev->dev, priv->irq, xlp9xx_i2c_isr, 0,
|
pdev->name, priv);
|
if (err) {
|
dev_err(&pdev->dev, "IRQ request failed!\n");
|
return err;
|
}
|
|
init_completion(&priv->msg_complete);
|
priv->adapter.dev.parent = &pdev->dev;
|
priv->adapter.algo = &xlp9xx_i2c_algo;
|
priv->adapter.class = I2C_CLASS_HWMON;
|
ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
|
priv->adapter.dev.of_node = pdev->dev.of_node;
|
priv->dev = &pdev->dev;
|
|
snprintf(priv->adapter.name, sizeof(priv->adapter.name), "xlp9xx-i2c");
|
i2c_set_adapdata(&priv->adapter, priv);
|
|
err = i2c_add_adapter(&priv->adapter);
|
if (err)
|
return err;
|
|
err = xlp9xx_i2c_smbus_setup(priv, pdev);
|
if (err)
|
dev_dbg(&pdev->dev, "No active SMBus alert %d\n", err);
|
|
platform_set_drvdata(pdev, priv);
|
dev_dbg(&pdev->dev, "I2C bus:%d added\n", priv->adapter.nr);
|
|
return 0;
|
}
|
|
static int xlp9xx_i2c_remove(struct platform_device *pdev)
|
{
|
struct xlp9xx_i2c_dev *priv;
|
|
priv = platform_get_drvdata(pdev);
|
xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
|
synchronize_irq(priv->irq);
|
i2c_del_adapter(&priv->adapter);
|
xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, 0);
|
|
return 0;
|
}
|
|
static const struct of_device_id xlp9xx_i2c_of_match[] = {
|
{ .compatible = "netlogic,xlp980-i2c", },
|
{ /* sentinel */ },
|
};
|
MODULE_DEVICE_TABLE(of, xlp9xx_i2c_of_match);
|
|
#ifdef CONFIG_ACPI
|
static const struct acpi_device_id xlp9xx_i2c_acpi_ids[] = {
|
{"BRCM9007", 0},
|
{"CAV9007", 0},
|
{}
|
};
|
MODULE_DEVICE_TABLE(acpi, xlp9xx_i2c_acpi_ids);
|
#endif
|
|
static struct platform_driver xlp9xx_i2c_driver = {
|
.probe = xlp9xx_i2c_probe,
|
.remove = xlp9xx_i2c_remove,
|
.driver = {
|
.name = "xlp9xx-i2c",
|
.of_match_table = xlp9xx_i2c_of_match,
|
.acpi_match_table = ACPI_PTR(xlp9xx_i2c_acpi_ids),
|
},
|
};
|
|
module_platform_driver(xlp9xx_i2c_driver);
|
|
MODULE_AUTHOR("Subhendu Sekhar Behera <sbehera@broadcom.com>");
|
MODULE_DESCRIPTION("XLP9XX/5XX I2C Bus Controller Driver");
|
MODULE_LICENSE("GPL v2");
|
