// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Tegra host1x Channel
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*
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* Copyright (c) 2010-2013, NVIDIA Corporation.
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*/
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#include <linux/host1x.h>
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#include <linux/iommu.h>
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#include <linux/slab.h>
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#include <trace/events/host1x.h>
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#include "../channel.h"
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#include "../dev.h"
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#include "../intr.h"
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#include "../job.h"
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#define TRACE_MAX_LENGTH 128U
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static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,
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u32 offset, u32 words)
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{
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struct device *dev = cdma_to_channel(cdma)->dev;
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void *mem = NULL;
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if (host1x_debug_trace_cmdbuf)
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mem = host1x_bo_mmap(bo);
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if (mem) {
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u32 i;
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/*
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* Write in batches of 128 as there seems to be a limit
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* of how much you can output to ftrace at once.
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*/
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for (i = 0; i < words; i += TRACE_MAX_LENGTH) {
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u32 num_words = min(words - i, TRACE_MAX_LENGTH);
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offset += i * sizeof(u32);
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trace_host1x_cdma_push_gather(dev_name(dev), bo,
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num_words, offset,
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mem);
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}
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host1x_bo_munmap(bo, mem);
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}
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}
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static void submit_gathers(struct host1x_job *job)
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{
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struct host1x_cdma *cdma = &job->channel->cdma;
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#if HOST1X_HW < 6
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struct device *dev = job->channel->dev;
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#endif
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unsigned int i;
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for (i = 0; i < job->num_gathers; i++) {
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struct host1x_job_gather *g = &job->gathers[i];
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dma_addr_t addr = g->base + g->offset;
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u32 op2, op3;
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op2 = lower_32_bits(addr);
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op3 = upper_32_bits(addr);
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trace_write_gather(cdma, g->bo, g->offset, g->words);
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if (op3 != 0) {
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#if HOST1X_HW >= 6
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u32 op1 = host1x_opcode_gather_wide(g->words);
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u32 op4 = HOST1X_OPCODE_NOP;
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host1x_cdma_push_wide(cdma, op1, op2, op3, op4);
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#else
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dev_err(dev, "invalid gather for push buffer %pad\n",
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&addr);
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continue;
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#endif
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} else {
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u32 op1 = host1x_opcode_gather(g->words);
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host1x_cdma_push(cdma, op1, op2);
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}
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}
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}
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static inline void synchronize_syncpt_base(struct host1x_job *job)
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{
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struct host1x *host = dev_get_drvdata(job->channel->dev->parent);
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struct host1x_syncpt *sp = host->syncpt + job->syncpt_id;
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unsigned int id;
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u32 value;
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value = host1x_syncpt_read_max(sp);
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id = sp->base->id;
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host1x_cdma_push(&job->channel->cdma,
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host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
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HOST1X_UCLASS_LOAD_SYNCPT_BASE, 1),
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HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(id) |
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HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(value));
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}
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static void host1x_channel_set_streamid(struct host1x_channel *channel)
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{
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#if HOST1X_HW >= 6
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u32 sid = 0x7f;
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#ifdef CONFIG_IOMMU_API
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struct iommu_fwspec *spec = dev_iommu_fwspec_get(channel->dev->parent);
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if (spec)
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sid = spec->ids[0] & 0xffff;
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#endif
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host1x_ch_writel(channel, sid, HOST1X_CHANNEL_SMMU_STREAMID);
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#endif
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}
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static int channel_submit(struct host1x_job *job)
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{
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struct host1x_channel *ch = job->channel;
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struct host1x_syncpt *sp;
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u32 user_syncpt_incrs = job->syncpt_incrs;
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u32 prev_max = 0;
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u32 syncval;
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int err;
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struct host1x_waitlist *completed_waiter = NULL;
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struct host1x *host = dev_get_drvdata(ch->dev->parent);
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sp = host->syncpt + job->syncpt_id;
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trace_host1x_channel_submit(dev_name(ch->dev),
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job->num_gathers, job->num_relocs,
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job->syncpt_id, job->syncpt_incrs);
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/* before error checks, return current max */
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prev_max = job->syncpt_end = host1x_syncpt_read_max(sp);
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/* get submit lock */
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err = mutex_lock_interruptible(&ch->submitlock);
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if (err)
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goto error;
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completed_waiter = kzalloc(sizeof(*completed_waiter), GFP_KERNEL);
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if (!completed_waiter) {
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mutex_unlock(&ch->submitlock);
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err = -ENOMEM;
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goto error;
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}
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host1x_channel_set_streamid(ch);
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/* begin a CDMA submit */
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err = host1x_cdma_begin(&ch->cdma, job);
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if (err) {
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mutex_unlock(&ch->submitlock);
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goto error;
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}
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if (job->serialize) {
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/*
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* Force serialization by inserting a host wait for the
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* previous job to finish before this one can commence.
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*/
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host1x_cdma_push(&ch->cdma,
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host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
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host1x_uclass_wait_syncpt_r(), 1),
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host1x_class_host_wait_syncpt(job->syncpt_id,
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host1x_syncpt_read_max(sp)));
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}
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/* Synchronize base register to allow using it for relative waiting */
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if (sp->base)
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synchronize_syncpt_base(job);
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syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
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host1x_hw_syncpt_assign_to_channel(host, sp, ch);
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job->syncpt_end = syncval;
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/* add a setclass for modules that require it */
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if (job->class)
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host1x_cdma_push(&ch->cdma,
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host1x_opcode_setclass(job->class, 0, 0),
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HOST1X_OPCODE_NOP);
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submit_gathers(job);
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/* end CDMA submit & stash pinned hMems into sync queue */
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host1x_cdma_end(&ch->cdma, job);
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trace_host1x_channel_submitted(dev_name(ch->dev), prev_max, syncval);
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/* schedule a submit complete interrupt */
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err = host1x_intr_add_action(host, sp, syncval,
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HOST1X_INTR_ACTION_SUBMIT_COMPLETE, ch,
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completed_waiter, NULL);
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completed_waiter = NULL;
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WARN(err, "Failed to set submit complete interrupt");
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mutex_unlock(&ch->submitlock);
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return 0;
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error:
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kfree(completed_waiter);
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return err;
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}
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static void enable_gather_filter(struct host1x *host,
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struct host1x_channel *ch)
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{
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#if HOST1X_HW >= 6
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u32 val;
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if (!host->hv_regs)
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return;
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val = host1x_hypervisor_readl(
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host, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32));
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val |= BIT(ch->id % 32);
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host1x_hypervisor_writel(
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host, val, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32));
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#elif HOST1X_HW >= 4
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host1x_ch_writel(ch,
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HOST1X_CHANNEL_CHANNELCTRL_KERNEL_FILTER_GBUFFER(1),
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HOST1X_CHANNEL_CHANNELCTRL);
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#endif
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}
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static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
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unsigned int index)
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{
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#if HOST1X_HW < 6
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ch->regs = dev->regs + index * 0x4000;
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#else
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ch->regs = dev->regs + index * 0x100;
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#endif
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enable_gather_filter(dev, ch);
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return 0;
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}
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static const struct host1x_channel_ops host1x_channel_ops = {
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.init = host1x_channel_init,
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.submit = channel_submit,
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};
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