// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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*/
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#include <linux/pci.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_fourcc.h>
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#include "bochs.h"
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/* ---------------------------------------------------------------------- */
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static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val)
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{
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if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df))
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return;
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if (bochs->mmio) {
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int offset = ioport - 0x3c0 + 0x400;
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writeb(val, bochs->mmio + offset);
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} else {
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outb(val, ioport);
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}
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}
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static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg)
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{
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u16 ret = 0;
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if (bochs->mmio) {
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int offset = 0x500 + (reg << 1);
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ret = readw(bochs->mmio + offset);
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} else {
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outw(reg, VBE_DISPI_IOPORT_INDEX);
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ret = inw(VBE_DISPI_IOPORT_DATA);
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}
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return ret;
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}
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static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val)
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{
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if (bochs->mmio) {
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int offset = 0x500 + (reg << 1);
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writew(val, bochs->mmio + offset);
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} else {
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outw(reg, VBE_DISPI_IOPORT_INDEX);
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outw(val, VBE_DISPI_IOPORT_DATA);
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}
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}
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static void bochs_hw_set_big_endian(struct bochs_device *bochs)
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{
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if (bochs->qext_size < 8)
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return;
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writel(0xbebebebe, bochs->mmio + 0x604);
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}
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static void bochs_hw_set_little_endian(struct bochs_device *bochs)
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{
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if (bochs->qext_size < 8)
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return;
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writel(0x1e1e1e1e, bochs->mmio + 0x604);
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}
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#ifdef __BIG_ENDIAN
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#define bochs_hw_set_native_endian(_b) bochs_hw_set_big_endian(_b)
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#else
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#define bochs_hw_set_native_endian(_b) bochs_hw_set_little_endian(_b)
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#endif
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static int bochs_get_edid_block(void *data, u8 *buf,
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unsigned int block, size_t len)
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{
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struct bochs_device *bochs = data;
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size_t i, start = block * EDID_LENGTH;
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if (start + len > 0x400 /* vga register offset */)
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return -1;
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for (i = 0; i < len; i++) {
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buf[i] = readb(bochs->mmio + start + i);
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}
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return 0;
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}
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int bochs_hw_load_edid(struct bochs_device *bochs)
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{
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u8 header[8];
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if (!bochs->mmio)
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return -1;
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/* check header to detect whenever edid support is enabled in qemu */
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bochs_get_edid_block(bochs, header, 0, ARRAY_SIZE(header));
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if (drm_edid_header_is_valid(header) != 8)
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return -1;
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kfree(bochs->edid);
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bochs->edid = drm_do_get_edid(&bochs->connector,
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bochs_get_edid_block, bochs);
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if (bochs->edid == NULL)
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return -1;
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return 0;
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}
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int bochs_hw_init(struct drm_device *dev)
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{
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struct bochs_device *bochs = dev->dev_private;
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struct pci_dev *pdev = dev->pdev;
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unsigned long addr, size, mem, ioaddr, iosize;
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u16 id;
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if (pdev->resource[2].flags & IORESOURCE_MEM) {
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/* mmio bar with vga and bochs registers present */
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if (pci_request_region(pdev, 2, "bochs-drm") != 0) {
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DRM_ERROR("Cannot request mmio region\n");
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return -EBUSY;
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}
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ioaddr = pci_resource_start(pdev, 2);
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iosize = pci_resource_len(pdev, 2);
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bochs->mmio = ioremap(ioaddr, iosize);
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if (bochs->mmio == NULL) {
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DRM_ERROR("Cannot map mmio region\n");
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return -ENOMEM;
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}
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} else {
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ioaddr = VBE_DISPI_IOPORT_INDEX;
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iosize = 2;
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if (!request_region(ioaddr, iosize, "bochs-drm")) {
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DRM_ERROR("Cannot request ioports\n");
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return -EBUSY;
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}
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bochs->ioports = 1;
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}
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id = bochs_dispi_read(bochs, VBE_DISPI_INDEX_ID);
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mem = bochs_dispi_read(bochs, VBE_DISPI_INDEX_VIDEO_MEMORY_64K)
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* 64 * 1024;
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if ((id & 0xfff0) != VBE_DISPI_ID0) {
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DRM_ERROR("ID mismatch\n");
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return -ENODEV;
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}
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if ((pdev->resource[0].flags & IORESOURCE_MEM) == 0)
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return -ENODEV;
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addr = pci_resource_start(pdev, 0);
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size = pci_resource_len(pdev, 0);
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if (addr == 0)
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return -ENODEV;
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if (size != mem) {
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DRM_ERROR("Size mismatch: pci=%ld, bochs=%ld\n",
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size, mem);
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size = min(size, mem);
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}
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if (pci_request_region(pdev, 0, "bochs-drm") != 0)
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DRM_WARN("Cannot request framebuffer, boot fb still active?\n");
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bochs->fb_map = ioremap(addr, size);
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if (bochs->fb_map == NULL) {
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DRM_ERROR("Cannot map framebuffer\n");
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return -ENOMEM;
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}
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bochs->fb_base = addr;
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bochs->fb_size = size;
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DRM_INFO("Found bochs VGA, ID 0x%x.\n", id);
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DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n",
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size / 1024, addr,
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bochs->ioports ? "ioports" : "mmio",
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ioaddr);
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if (bochs->mmio && pdev->revision >= 2) {
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bochs->qext_size = readl(bochs->mmio + 0x600);
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if (bochs->qext_size < 4 || bochs->qext_size > iosize) {
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bochs->qext_size = 0;
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goto noext;
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}
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DRM_DEBUG("Found qemu ext regs, size %ld\n",
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bochs->qext_size);
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bochs_hw_set_native_endian(bochs);
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}
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noext:
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return 0;
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}
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void bochs_hw_fini(struct drm_device *dev)
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{
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struct bochs_device *bochs = dev->dev_private;
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/* TODO: shot down existing vram mappings */
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if (bochs->mmio)
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iounmap(bochs->mmio);
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if (bochs->ioports)
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release_region(VBE_DISPI_IOPORT_INDEX, 2);
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if (bochs->fb_map)
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iounmap(bochs->fb_map);
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pci_release_regions(dev->pdev);
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kfree(bochs->edid);
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}
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void bochs_hw_setmode(struct bochs_device *bochs,
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struct drm_display_mode *mode)
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{
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int idx;
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if (!drm_dev_enter(bochs->dev, &idx))
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return;
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bochs->xres = mode->hdisplay;
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bochs->yres = mode->vdisplay;
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bochs->bpp = 32;
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bochs->stride = mode->hdisplay * (bochs->bpp / 8);
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bochs->yres_virtual = bochs->fb_size / bochs->stride;
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DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n",
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bochs->xres, bochs->yres, bochs->bpp,
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bochs->yres_virtual);
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bochs_vga_writeb(bochs, 0x3c0, 0x20); /* unblank */
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE, 0);
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP, bochs->bpp);
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_XRES, bochs->xres);
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_YRES, bochs->yres);
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_BANK, 0);
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, bochs->xres);
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_HEIGHT,
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bochs->yres_virtual);
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, 0);
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, 0);
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,
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VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED);
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drm_dev_exit(idx);
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}
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void bochs_hw_setformat(struct bochs_device *bochs,
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const struct drm_format_info *format)
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{
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int idx;
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if (!drm_dev_enter(bochs->dev, &idx))
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return;
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DRM_DEBUG_DRIVER("format %c%c%c%c\n",
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(format->format >> 0) & 0xff,
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(format->format >> 8) & 0xff,
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(format->format >> 16) & 0xff,
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(format->format >> 24) & 0xff);
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switch (format->format) {
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case DRM_FORMAT_XRGB8888:
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bochs_hw_set_little_endian(bochs);
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break;
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case DRM_FORMAT_BGRX8888:
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bochs_hw_set_big_endian(bochs);
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break;
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default:
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/* should not happen */
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DRM_ERROR("%s: Huh? Got framebuffer format 0x%x",
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__func__, format->format);
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break;
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}
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drm_dev_exit(idx);
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}
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void bochs_hw_setbase(struct bochs_device *bochs,
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int x, int y, int stride, u64 addr)
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{
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unsigned long offset;
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unsigned int vx, vy, vwidth, idx;
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if (!drm_dev_enter(bochs->dev, &idx))
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return;
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bochs->stride = stride;
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offset = (unsigned long)addr +
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y * bochs->stride +
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x * (bochs->bpp / 8);
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vy = offset / bochs->stride;
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vx = (offset % bochs->stride) * 8 / bochs->bpp;
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vwidth = stride * 8 / bochs->bpp;
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DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n",
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x, y, addr, offset, vx, vy);
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth);
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx);
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bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy);
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drm_dev_exit(idx);
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}
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