/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Register bitfield descriptions for Pondicherry2 memory controller.
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*
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* Copyright (c) 2016, Intel Corporation.
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*/
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#ifndef _PND2_REGS_H
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#define _PND2_REGS_H
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struct b_cr_touud_lo_pci {
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u32 lock : 1;
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u32 reserved_1 : 19;
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u32 touud : 12;
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};
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#define b_cr_touud_lo_pci_port 0x4c
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#define b_cr_touud_lo_pci_offset 0xa8
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#define b_cr_touud_lo_pci_r_opcode 0x04
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struct b_cr_touud_hi_pci {
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u32 touud : 7;
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u32 reserved_0 : 25;
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};
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#define b_cr_touud_hi_pci_port 0x4c
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#define b_cr_touud_hi_pci_offset 0xac
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#define b_cr_touud_hi_pci_r_opcode 0x04
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struct b_cr_tolud_pci {
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u32 lock : 1;
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u32 reserved_0 : 19;
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u32 tolud : 12;
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};
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#define b_cr_tolud_pci_port 0x4c
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#define b_cr_tolud_pci_offset 0xbc
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#define b_cr_tolud_pci_r_opcode 0x04
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struct b_cr_mchbar_lo_pci {
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u32 enable : 1;
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u32 pad_3_1 : 3;
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u32 pad_14_4: 11;
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u32 base: 17;
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};
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struct b_cr_mchbar_hi_pci {
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u32 base : 7;
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u32 pad_31_7 : 25;
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};
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/* Symmetric region */
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struct b_cr_slice_channel_hash {
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u64 slice_1_disabled : 1;
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u64 hvm_mode : 1;
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u64 interleave_mode : 2;
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u64 slice_0_mem_disabled : 1;
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u64 reserved_0 : 1;
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u64 slice_hash_mask : 14;
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u64 reserved_1 : 11;
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u64 enable_pmi_dual_data_mode : 1;
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u64 ch_1_disabled : 1;
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u64 reserved_2 : 1;
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u64 sym_slice0_channel_enabled : 2;
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u64 sym_slice1_channel_enabled : 2;
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u64 ch_hash_mask : 14;
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u64 reserved_3 : 11;
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u64 lock : 1;
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};
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#define b_cr_slice_channel_hash_port 0x4c
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#define b_cr_slice_channel_hash_offset 0x4c58
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#define b_cr_slice_channel_hash_r_opcode 0x06
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struct b_cr_mot_out_base_mchbar {
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u32 reserved_0 : 14;
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u32 mot_out_base : 15;
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u32 reserved_1 : 1;
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u32 tr_en : 1;
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u32 imr_en : 1;
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};
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#define b_cr_mot_out_base_mchbar_port 0x4c
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#define b_cr_mot_out_base_mchbar_offset 0x6af0
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#define b_cr_mot_out_base_mchbar_r_opcode 0x00
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struct b_cr_mot_out_mask_mchbar {
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u32 reserved_0 : 14;
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u32 mot_out_mask : 15;
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u32 reserved_1 : 1;
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u32 ia_iwb_en : 1;
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u32 gt_iwb_en : 1;
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};
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#define b_cr_mot_out_mask_mchbar_port 0x4c
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#define b_cr_mot_out_mask_mchbar_offset 0x6af4
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#define b_cr_mot_out_mask_mchbar_r_opcode 0x00
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struct b_cr_asym_mem_region0_mchbar {
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u32 pad : 4;
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u32 slice0_asym_base : 11;
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u32 pad_18_15 : 4;
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u32 slice0_asym_limit : 11;
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u32 slice0_asym_channel_select : 1;
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u32 slice0_asym_enable : 1;
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};
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#define b_cr_asym_mem_region0_mchbar_port 0x4c
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#define b_cr_asym_mem_region0_mchbar_offset 0x6e40
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#define b_cr_asym_mem_region0_mchbar_r_opcode 0x00
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struct b_cr_asym_mem_region1_mchbar {
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u32 pad : 4;
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u32 slice1_asym_base : 11;
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u32 pad_18_15 : 4;
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u32 slice1_asym_limit : 11;
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u32 slice1_asym_channel_select : 1;
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u32 slice1_asym_enable : 1;
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};
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#define b_cr_asym_mem_region1_mchbar_port 0x4c
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#define b_cr_asym_mem_region1_mchbar_offset 0x6e44
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#define b_cr_asym_mem_region1_mchbar_r_opcode 0x00
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/* Some bit fields moved in above two structs on Denverton */
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struct b_cr_asym_mem_region_denverton {
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u32 pad : 4;
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u32 slice_asym_base : 8;
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u32 pad_19_12 : 8;
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u32 slice_asym_limit : 8;
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u32 pad_28_30 : 3;
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u32 slice_asym_enable : 1;
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};
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struct b_cr_asym_2way_mem_region_mchbar {
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u32 pad : 2;
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u32 asym_2way_intlv_mode : 2;
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u32 asym_2way_base : 11;
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u32 pad_16_15 : 2;
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u32 asym_2way_limit : 11;
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u32 pad_30_28 : 3;
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u32 asym_2way_interleave_enable : 1;
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};
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#define b_cr_asym_2way_mem_region_mchbar_port 0x4c
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#define b_cr_asym_2way_mem_region_mchbar_offset 0x6e50
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#define b_cr_asym_2way_mem_region_mchbar_r_opcode 0x00
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/* Apollo Lake d-unit */
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struct d_cr_drp0 {
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u32 rken0 : 1;
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u32 rken1 : 1;
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u32 ddmen : 1;
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u32 rsvd3 : 1;
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u32 dwid : 2;
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u32 dden : 3;
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u32 rsvd13_9 : 5;
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u32 rsien : 1;
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u32 bahen : 1;
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u32 rsvd18_16 : 3;
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u32 caswizzle : 2;
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u32 eccen : 1;
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u32 dramtype : 3;
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u32 blmode : 3;
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u32 addrdec : 2;
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u32 dramdevice_pr : 2;
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};
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#define d_cr_drp0_offset 0x1400
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#define d_cr_drp0_r_opcode 0x00
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/* Denverton d-unit */
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struct d_cr_dsch {
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u32 ch0en : 1;
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u32 ch1en : 1;
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u32 ddr4en : 1;
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u32 coldwake : 1;
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u32 newbypdis : 1;
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u32 chan_width : 1;
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u32 rsvd6_6 : 1;
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u32 ooodis : 1;
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u32 rsvd18_8 : 11;
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u32 ic : 1;
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u32 rsvd31_20 : 12;
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};
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#define d_cr_dsch_port 0x16
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#define d_cr_dsch_offset 0x0
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#define d_cr_dsch_r_opcode 0x0
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struct d_cr_ecc_ctrl {
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u32 eccen : 1;
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u32 rsvd31_1 : 31;
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};
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#define d_cr_ecc_ctrl_offset 0x180
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#define d_cr_ecc_ctrl_r_opcode 0x0
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struct d_cr_drp {
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u32 rken0 : 1;
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u32 rken1 : 1;
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u32 rken2 : 1;
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u32 rken3 : 1;
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u32 dimmdwid0 : 2;
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u32 dimmdden0 : 2;
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u32 dimmdwid1 : 2;
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u32 dimmdden1 : 2;
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u32 rsvd15_12 : 4;
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u32 dimmflip : 1;
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u32 rsvd31_17 : 15;
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};
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#define d_cr_drp_offset 0x158
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#define d_cr_drp_r_opcode 0x0
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struct d_cr_dmap {
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u32 ba0 : 5;
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u32 ba1 : 5;
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u32 bg0 : 5; /* if ddr3, ba2 = bg0 */
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u32 bg1 : 5; /* if ddr3, ba3 = bg1 */
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u32 rs0 : 5;
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u32 rs1 : 5;
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u32 rsvd : 2;
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};
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#define d_cr_dmap_offset 0x174
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#define d_cr_dmap_r_opcode 0x0
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struct d_cr_dmap1 {
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u32 ca11 : 6;
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u32 bxor : 1;
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u32 rsvd : 25;
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};
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#define d_cr_dmap1_offset 0xb4
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#define d_cr_dmap1_r_opcode 0x0
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struct d_cr_dmap2 {
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u32 row0 : 5;
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u32 row1 : 5;
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u32 row2 : 5;
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u32 row3 : 5;
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u32 row4 : 5;
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u32 row5 : 5;
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u32 rsvd : 2;
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};
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#define d_cr_dmap2_offset 0x148
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#define d_cr_dmap2_r_opcode 0x0
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struct d_cr_dmap3 {
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u32 row6 : 5;
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u32 row7 : 5;
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u32 row8 : 5;
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u32 row9 : 5;
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u32 row10 : 5;
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u32 row11 : 5;
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u32 rsvd : 2;
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};
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#define d_cr_dmap3_offset 0x14c
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#define d_cr_dmap3_r_opcode 0x0
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struct d_cr_dmap4 {
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u32 row12 : 5;
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u32 row13 : 5;
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u32 row14 : 5;
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u32 row15 : 5;
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u32 row16 : 5;
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u32 row17 : 5;
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u32 rsvd : 2;
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};
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#define d_cr_dmap4_offset 0x150
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#define d_cr_dmap4_r_opcode 0x0
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struct d_cr_dmap5 {
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u32 ca3 : 4;
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u32 ca4 : 4;
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u32 ca5 : 4;
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u32 ca6 : 4;
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u32 ca7 : 4;
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u32 ca8 : 4;
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u32 ca9 : 4;
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u32 rsvd : 4;
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};
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#define d_cr_dmap5_offset 0x154
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#define d_cr_dmap5_r_opcode 0x0
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#endif /* _PND2_REGS_H */
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