// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Core driver for the Intel integrated DMA 64-bit
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*
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* Copyright (C) 2015 Intel Corporation
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/dma/idma64.h>
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#include "idma64.h"
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/* For now we support only two channels */
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#define IDMA64_NR_CHAN 2
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/* ---------------------------------------------------------------------- */
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static struct device *chan2dev(struct dma_chan *chan)
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{
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return &chan->dev->device;
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}
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/* ---------------------------------------------------------------------- */
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static void idma64_off(struct idma64 *idma64)
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{
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unsigned short count = 100;
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dma_writel(idma64, CFG, 0);
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channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
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channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask);
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channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask);
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channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask);
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channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
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do {
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cpu_relax();
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} while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count);
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}
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static void idma64_on(struct idma64 *idma64)
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{
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dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
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}
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/* ---------------------------------------------------------------------- */
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static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
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{
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u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
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u32 cfglo = 0;
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/* Set default burst alignment */
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cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
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channel_writel(idma64c, CFG_LO, cfglo);
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channel_writel(idma64c, CFG_HI, cfghi);
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/* Enable interrupts */
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channel_set_bit(idma64, MASK(XFER), idma64c->mask);
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channel_set_bit(idma64, MASK(ERROR), idma64c->mask);
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/*
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* Enforce the controller to be turned on.
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*
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* The iDMA is turned off in ->probe() and looses context during system
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* suspend / resume cycle. That's why we have to enable it each time we
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* use it.
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*/
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idma64_on(idma64);
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}
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static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c)
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{
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channel_clear_bit(idma64, CH_EN, idma64c->mask);
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}
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static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c)
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{
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struct idma64_desc *desc = idma64c->desc;
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struct idma64_hw_desc *hw = &desc->hw[0];
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channel_writeq(idma64c, SAR, 0);
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channel_writeq(idma64c, DAR, 0);
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channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL));
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channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
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channel_writeq(idma64c, LLP, hw->llp);
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channel_set_bit(idma64, CH_EN, idma64c->mask);
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}
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static void idma64_stop_transfer(struct idma64_chan *idma64c)
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{
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struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
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idma64_chan_stop(idma64, idma64c);
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}
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static void idma64_start_transfer(struct idma64_chan *idma64c)
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{
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struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
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struct virt_dma_desc *vdesc;
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/* Get the next descriptor */
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vdesc = vchan_next_desc(&idma64c->vchan);
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if (!vdesc) {
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idma64c->desc = NULL;
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return;
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}
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list_del(&vdesc->node);
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idma64c->desc = to_idma64_desc(vdesc);
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/* Configure the channel */
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idma64_chan_init(idma64, idma64c);
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/* Start the channel with a new descriptor */
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idma64_chan_start(idma64, idma64c);
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}
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/* ---------------------------------------------------------------------- */
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static void idma64_chan_irq(struct idma64 *idma64, unsigned short c,
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u32 status_err, u32 status_xfer)
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{
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struct idma64_chan *idma64c = &idma64->chan[c];
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struct idma64_desc *desc;
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spin_lock(&idma64c->vchan.lock);
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desc = idma64c->desc;
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if (desc) {
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if (status_err & (1 << c)) {
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dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
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desc->status = DMA_ERROR;
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} else if (status_xfer & (1 << c)) {
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dma_writel(idma64, CLEAR(XFER), idma64c->mask);
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desc->status = DMA_COMPLETE;
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vchan_cookie_complete(&desc->vdesc);
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idma64_start_transfer(idma64c);
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}
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/* idma64_start_transfer() updates idma64c->desc */
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if (idma64c->desc == NULL || desc->status == DMA_ERROR)
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idma64_stop_transfer(idma64c);
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}
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spin_unlock(&idma64c->vchan.lock);
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}
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static irqreturn_t idma64_irq(int irq, void *dev)
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{
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struct idma64 *idma64 = dev;
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u32 status = dma_readl(idma64, STATUS_INT);
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u32 status_xfer;
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u32 status_err;
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unsigned short i;
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dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status);
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/* Check if we have any interrupt from the DMA controller */
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if (!status)
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return IRQ_NONE;
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status_xfer = dma_readl(idma64, RAW(XFER));
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status_err = dma_readl(idma64, RAW(ERROR));
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for (i = 0; i < idma64->dma.chancnt; i++)
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idma64_chan_irq(idma64, i, status_err, status_xfer);
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return IRQ_HANDLED;
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}
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/* ---------------------------------------------------------------------- */
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static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc)
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{
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struct idma64_desc *desc;
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desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
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if (!desc)
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return NULL;
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desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT);
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if (!desc->hw) {
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kfree(desc);
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return NULL;
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}
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return desc;
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}
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static void idma64_desc_free(struct idma64_chan *idma64c,
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struct idma64_desc *desc)
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{
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struct idma64_hw_desc *hw;
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if (desc->ndesc) {
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unsigned int i = desc->ndesc;
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do {
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hw = &desc->hw[--i];
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dma_pool_free(idma64c->pool, hw->lli, hw->llp);
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} while (i);
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}
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kfree(desc->hw);
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kfree(desc);
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}
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static void idma64_vdesc_free(struct virt_dma_desc *vdesc)
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{
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struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan);
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idma64_desc_free(idma64c, to_idma64_desc(vdesc));
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}
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static void idma64_hw_desc_fill(struct idma64_hw_desc *hw,
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struct dma_slave_config *config,
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enum dma_transfer_direction direction, u64 llp)
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{
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struct idma64_lli *lli = hw->lli;
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u64 sar, dar;
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u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len);
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u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN;
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u32 src_width, dst_width;
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if (direction == DMA_MEM_TO_DEV) {
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sar = hw->phys;
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dar = config->dst_addr;
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ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
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IDMA64C_CTLL_FC_M2P;
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src_width = __ffs(sar | hw->len | 4);
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dst_width = __ffs(config->dst_addr_width);
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} else { /* DMA_DEV_TO_MEM */
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sar = config->src_addr;
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dar = hw->phys;
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ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
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IDMA64C_CTLL_FC_P2M;
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src_width = __ffs(config->src_addr_width);
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dst_width = __ffs(dar | hw->len | 4);
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}
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lli->sar = sar;
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lli->dar = dar;
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lli->ctlhi = ctlhi;
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lli->ctllo = ctllo |
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IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) |
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IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) |
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IDMA64C_CTLL_DST_WIDTH(dst_width) |
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IDMA64C_CTLL_SRC_WIDTH(src_width);
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lli->llp = llp;
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}
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static void idma64_desc_fill(struct idma64_chan *idma64c,
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struct idma64_desc *desc)
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{
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struct dma_slave_config *config = &idma64c->config;
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unsigned int i = desc->ndesc;
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struct idma64_hw_desc *hw = &desc->hw[i - 1];
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struct idma64_lli *lli = hw->lli;
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u64 llp = 0;
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/* Fill the hardware descriptors and link them to a list */
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do {
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hw = &desc->hw[--i];
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idma64_hw_desc_fill(hw, config, desc->direction, llp);
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llp = hw->llp;
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desc->length += hw->len;
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} while (i);
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/* Trigger an interrupt after the last block is transfered */
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lli->ctllo |= IDMA64C_CTLL_INT_EN;
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/* Disable LLP transfer in the last block */
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lli->ctllo &= ~(IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
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}
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static struct dma_async_tx_descriptor *idma64_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct idma64_chan *idma64c = to_idma64_chan(chan);
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struct idma64_desc *desc;
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struct scatterlist *sg;
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unsigned int i;
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desc = idma64_alloc_desc(sg_len);
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if (!desc)
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return NULL;
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for_each_sg(sgl, sg, sg_len, i) {
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struct idma64_hw_desc *hw = &desc->hw[i];
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/* Allocate DMA capable memory for hardware descriptor */
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hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp);
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if (!hw->lli) {
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desc->ndesc = i;
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idma64_desc_free(idma64c, desc);
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return NULL;
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}
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hw->phys = sg_dma_address(sg);
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hw->len = sg_dma_len(sg);
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}
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desc->ndesc = sg_len;
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desc->direction = direction;
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desc->status = DMA_IN_PROGRESS;
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idma64_desc_fill(idma64c, desc);
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return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags);
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}
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static void idma64_issue_pending(struct dma_chan *chan)
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{
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struct idma64_chan *idma64c = to_idma64_chan(chan);
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unsigned long flags;
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spin_lock_irqsave(&idma64c->vchan.lock, flags);
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if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc)
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idma64_start_transfer(idma64c);
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spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
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}
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static size_t idma64_active_desc_size(struct idma64_chan *idma64c)
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{
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struct idma64_desc *desc = idma64c->desc;
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struct idma64_hw_desc *hw;
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size_t bytes = desc->length;
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u64 llp = channel_readq(idma64c, LLP);
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u32 ctlhi = channel_readl(idma64c, CTL_HI);
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unsigned int i = 0;
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do {
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hw = &desc->hw[i];
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if (hw->llp == llp)
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break;
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bytes -= hw->len;
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} while (++i < desc->ndesc);
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if (!i)
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return bytes;
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/* The current chunk is not fully transfered yet */
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bytes += desc->hw[--i].len;
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return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi);
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}
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static enum dma_status idma64_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie, struct dma_tx_state *state)
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{
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struct idma64_chan *idma64c = to_idma64_chan(chan);
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struct virt_dma_desc *vdesc;
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enum dma_status status;
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size_t bytes;
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unsigned long flags;
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status = dma_cookie_status(chan, cookie, state);
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if (status == DMA_COMPLETE)
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return status;
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spin_lock_irqsave(&idma64c->vchan.lock, flags);
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vdesc = vchan_find_desc(&idma64c->vchan, cookie);
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if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) {
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bytes = idma64_active_desc_size(idma64c);
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dma_set_residue(state, bytes);
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status = idma64c->desc->status;
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} else if (vdesc) {
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bytes = to_idma64_desc(vdesc)->length;
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dma_set_residue(state, bytes);
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}
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spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
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return status;
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}
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static void convert_burst(u32 *maxburst)
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{
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if (*maxburst)
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*maxburst = __fls(*maxburst);
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else
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*maxburst = 0;
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}
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static int idma64_slave_config(struct dma_chan *chan,
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struct dma_slave_config *config)
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{
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struct idma64_chan *idma64c = to_idma64_chan(chan);
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memcpy(&idma64c->config, config, sizeof(idma64c->config));
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convert_burst(&idma64c->config.src_maxburst);
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convert_burst(&idma64c->config.dst_maxburst);
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return 0;
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}
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static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain)
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{
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unsigned short count = 100;
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u32 cfglo;
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cfglo = channel_readl(idma64c, CFG_LO);
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if (drain)
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cfglo |= IDMA64C_CFGL_CH_DRAIN;
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else
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cfglo &= ~IDMA64C_CFGL_CH_DRAIN;
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channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
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do {
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udelay(1);
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cfglo = channel_readl(idma64c, CFG_LO);
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} while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count);
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}
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static void idma64_chan_activate(struct idma64_chan *idma64c)
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{
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u32 cfglo;
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cfglo = channel_readl(idma64c, CFG_LO);
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channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP);
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}
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static int idma64_pause(struct dma_chan *chan)
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{
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struct idma64_chan *idma64c = to_idma64_chan(chan);
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unsigned long flags;
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spin_lock_irqsave(&idma64c->vchan.lock, flags);
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if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
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idma64_chan_deactivate(idma64c, false);
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idma64c->desc->status = DMA_PAUSED;
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}
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spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
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return 0;
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}
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static int idma64_resume(struct dma_chan *chan)
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{
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struct idma64_chan *idma64c = to_idma64_chan(chan);
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unsigned long flags;
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spin_lock_irqsave(&idma64c->vchan.lock, flags);
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if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) {
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idma64c->desc->status = DMA_IN_PROGRESS;
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idma64_chan_activate(idma64c);
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}
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spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
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return 0;
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}
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static int idma64_terminate_all(struct dma_chan *chan)
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{
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struct idma64_chan *idma64c = to_idma64_chan(chan);
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unsigned long flags;
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LIST_HEAD(head);
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spin_lock_irqsave(&idma64c->vchan.lock, flags);
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idma64_chan_deactivate(idma64c, true);
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idma64_stop_transfer(idma64c);
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if (idma64c->desc) {
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idma64_vdesc_free(&idma64c->desc->vdesc);
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idma64c->desc = NULL;
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}
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vchan_get_all_descriptors(&idma64c->vchan, &head);
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spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
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vchan_dma_desc_free_list(&idma64c->vchan, &head);
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return 0;
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}
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static void idma64_synchronize(struct dma_chan *chan)
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{
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struct idma64_chan *idma64c = to_idma64_chan(chan);
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vchan_synchronize(&idma64c->vchan);
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}
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static int idma64_alloc_chan_resources(struct dma_chan *chan)
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{
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struct idma64_chan *idma64c = to_idma64_chan(chan);
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/* Create a pool of consistent memory blocks for hardware descriptors */
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idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)),
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chan->device->dev,
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sizeof(struct idma64_lli), 8, 0);
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if (!idma64c->pool) {
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dev_err(chan2dev(chan), "No memory for descriptors\n");
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return -ENOMEM;
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}
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return 0;
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}
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static void idma64_free_chan_resources(struct dma_chan *chan)
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{
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struct idma64_chan *idma64c = to_idma64_chan(chan);
|
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vchan_free_chan_resources(to_virt_chan(chan));
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dma_pool_destroy(idma64c->pool);
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idma64c->pool = NULL;
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}
|
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/* ---------------------------------------------------------------------- */
|
|
#define IDMA64_BUSWIDTHS \
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BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
|
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static int idma64_probe(struct idma64_chip *chip)
|
{
|
struct idma64 *idma64;
|
unsigned short nr_chan = IDMA64_NR_CHAN;
|
unsigned short i;
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int ret;
|
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idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL);
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if (!idma64)
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return -ENOMEM;
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idma64->regs = chip->regs;
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chip->idma64 = idma64;
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idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan),
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GFP_KERNEL);
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if (!idma64->chan)
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return -ENOMEM;
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idma64->all_chan_mask = (1 << nr_chan) - 1;
|
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/* Turn off iDMA controller */
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idma64_off(idma64);
|
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ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED,
|
dev_name(chip->dev), idma64);
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if (ret)
|
return ret;
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|
INIT_LIST_HEAD(&idma64->dma.channels);
|
for (i = 0; i < nr_chan; i++) {
|
struct idma64_chan *idma64c = &idma64->chan[i];
|
|
idma64c->vchan.desc_free = idma64_vdesc_free;
|
vchan_init(&idma64c->vchan, &idma64->dma);
|
|
idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH;
|
idma64c->mask = BIT(i);
|
}
|
|
dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask);
|
dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask);
|
|
idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources;
|
idma64->dma.device_free_chan_resources = idma64_free_chan_resources;
|
|
idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg;
|
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idma64->dma.device_issue_pending = idma64_issue_pending;
|
idma64->dma.device_tx_status = idma64_tx_status;
|
|
idma64->dma.device_config = idma64_slave_config;
|
idma64->dma.device_pause = idma64_pause;
|
idma64->dma.device_resume = idma64_resume;
|
idma64->dma.device_terminate_all = idma64_terminate_all;
|
idma64->dma.device_synchronize = idma64_synchronize;
|
|
idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS;
|
idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS;
|
idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
|
|
idma64->dma.dev = chip->sysdev;
|
|
dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK);
|
|
ret = dma_async_device_register(&idma64->dma);
|
if (ret)
|
return ret;
|
|
dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n");
|
return 0;
|
}
|
|
static int idma64_remove(struct idma64_chip *chip)
|
{
|
struct idma64 *idma64 = chip->idma64;
|
unsigned short i;
|
|
dma_async_device_unregister(&idma64->dma);
|
|
/*
|
* Explicitly call devm_request_irq() to avoid the side effects with
|
* the scheduled tasklets.
|
*/
|
devm_free_irq(chip->dev, chip->irq, idma64);
|
|
for (i = 0; i < idma64->dma.chancnt; i++) {
|
struct idma64_chan *idma64c = &idma64->chan[i];
|
|
tasklet_kill(&idma64c->vchan.task);
|
}
|
|
return 0;
|
}
|
|
/* ---------------------------------------------------------------------- */
|
|
static int idma64_platform_probe(struct platform_device *pdev)
|
{
|
struct idma64_chip *chip;
|
struct device *dev = &pdev->dev;
|
struct device *sysdev = dev->parent;
|
struct resource *mem;
|
int ret;
|
|
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
|
if (!chip)
|
return -ENOMEM;
|
|
chip->irq = platform_get_irq(pdev, 0);
|
if (chip->irq < 0)
|
return chip->irq;
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
chip->regs = devm_ioremap_resource(dev, mem);
|
if (IS_ERR(chip->regs))
|
return PTR_ERR(chip->regs);
|
|
ret = dma_coerce_mask_and_coherent(sysdev, DMA_BIT_MASK(64));
|
if (ret)
|
return ret;
|
|
chip->dev = dev;
|
chip->sysdev = sysdev;
|
|
ret = idma64_probe(chip);
|
if (ret)
|
return ret;
|
|
platform_set_drvdata(pdev, chip);
|
return 0;
|
}
|
|
static int idma64_platform_remove(struct platform_device *pdev)
|
{
|
struct idma64_chip *chip = platform_get_drvdata(pdev);
|
|
return idma64_remove(chip);
|
}
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int idma64_pm_suspend(struct device *dev)
|
{
|
struct idma64_chip *chip = dev_get_drvdata(dev);
|
|
idma64_off(chip->idma64);
|
return 0;
|
}
|
|
static int idma64_pm_resume(struct device *dev)
|
{
|
struct idma64_chip *chip = dev_get_drvdata(dev);
|
|
idma64_on(chip->idma64);
|
return 0;
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
static const struct dev_pm_ops idma64_dev_pm_ops = {
|
SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume)
|
};
|
|
static struct platform_driver idma64_platform_driver = {
|
.probe = idma64_platform_probe,
|
.remove = idma64_platform_remove,
|
.driver = {
|
.name = LPSS_IDMA64_DRIVER_NAME,
|
.pm = &idma64_dev_pm_ops,
|
},
|
};
|
|
module_platform_driver(idma64_platform_driver);
|
|
MODULE_LICENSE("GPL v2");
|
MODULE_DESCRIPTION("iDMA64 core driver");
|
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
|
MODULE_ALIAS("platform:" LPSS_IDMA64_DRIVER_NAME);
|
