// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include "ccu_sdm.h"
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bool ccu_sdm_helper_is_enabled(struct ccu_common *common,
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struct ccu_sdm_internal *sdm)
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{
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if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
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return false;
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if (sdm->enable && !(readl(common->base + common->reg) & sdm->enable))
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return false;
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return !!(readl(common->base + sdm->tuning_reg) & sdm->tuning_enable);
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}
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void ccu_sdm_helper_enable(struct ccu_common *common,
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struct ccu_sdm_internal *sdm,
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unsigned long rate)
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{
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unsigned long flags;
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unsigned int i;
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u32 reg;
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if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
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return;
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/* Set the pattern */
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for (i = 0; i < sdm->table_size; i++)
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if (sdm->table[i].rate == rate)
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writel(sdm->table[i].pattern,
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common->base + sdm->tuning_reg);
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/* Make sure SDM is enabled */
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spin_lock_irqsave(common->lock, flags);
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reg = readl(common->base + sdm->tuning_reg);
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writel(reg | sdm->tuning_enable, common->base + sdm->tuning_reg);
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spin_unlock_irqrestore(common->lock, flags);
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spin_lock_irqsave(common->lock, flags);
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reg = readl(common->base + common->reg);
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writel(reg | sdm->enable, common->base + common->reg);
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spin_unlock_irqrestore(common->lock, flags);
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}
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void ccu_sdm_helper_disable(struct ccu_common *common,
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struct ccu_sdm_internal *sdm)
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{
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unsigned long flags;
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u32 reg;
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if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
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return;
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spin_lock_irqsave(common->lock, flags);
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reg = readl(common->base + common->reg);
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writel(reg & ~sdm->enable, common->base + common->reg);
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spin_unlock_irqrestore(common->lock, flags);
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spin_lock_irqsave(common->lock, flags);
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reg = readl(common->base + sdm->tuning_reg);
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writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg);
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spin_unlock_irqrestore(common->lock, flags);
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}
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/*
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* Sigma delta modulation provides a way to do fractional-N frequency
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* synthesis, in essence allowing the PLL to output any frequency
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* within its operational range. On earlier SoCs such as the A10/A20,
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* some PLLs support this. On later SoCs, all PLLs support this.
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*
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* The datasheets do not explain what the "wave top" and "wave bottom"
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* parameters mean or do, nor how to calculate the effective output
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* frequency. The only examples (and real world usage) are for the audio
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* PLL to generate 24.576 and 22.5792 MHz clock rates used by the audio
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* peripherals. The author lacks the underlying domain knowledge to
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* pursue this.
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*
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* The goal and function of the following code is to support the two
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* clock rates used by the audio subsystem, allowing for proper audio
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* playback and capture without any pitch or speed changes.
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*/
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bool ccu_sdm_helper_has_rate(struct ccu_common *common,
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struct ccu_sdm_internal *sdm,
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unsigned long rate)
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{
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unsigned int i;
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if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
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return false;
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for (i = 0; i < sdm->table_size; i++)
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if (sdm->table[i].rate == rate)
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return true;
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return false;
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}
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unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common,
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struct ccu_sdm_internal *sdm,
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u32 m, u32 n)
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{
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unsigned int i;
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u32 reg;
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pr_debug("%s: Read sigma-delta modulation setting\n",
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clk_hw_get_name(&common->hw));
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if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
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return 0;
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pr_debug("%s: clock is sigma-delta modulated\n",
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clk_hw_get_name(&common->hw));
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reg = readl(common->base + sdm->tuning_reg);
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pr_debug("%s: pattern reg is 0x%x",
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clk_hw_get_name(&common->hw), reg);
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for (i = 0; i < sdm->table_size; i++)
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if (sdm->table[i].pattern == reg &&
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sdm->table[i].m == m && sdm->table[i].n == n)
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return sdm->table[i].rate;
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/* We can't calculate the effective clock rate, so just fail. */
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return 0;
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}
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int ccu_sdm_helper_get_factors(struct ccu_common *common,
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struct ccu_sdm_internal *sdm,
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unsigned long rate,
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unsigned long *m, unsigned long *n)
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{
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unsigned int i;
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if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
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return -EINVAL;
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for (i = 0; i < sdm->table_size; i++)
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if (sdm->table[i].rate == rate) {
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*m = sdm->table[i].m;
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*n = sdm->table[i].n;
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return 0;
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}
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/* nothing found */
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return -EINVAL;
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}
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