// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*
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* Todo: - add support for the OF persistent properties
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*/
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/string.h>
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#include <linux/nvram.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/adb.h>
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#include <linux/pmu.h>
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#include <linux/memblock.h>
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#include <linux/completion.h>
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#include <linux/spinlock.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/nvram.h>
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#include "pmac.h"
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#define DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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#define NVRAM_SIZE 0x2000 /* 8kB of non-volatile RAM */
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#define CORE99_SIGNATURE 0x5a
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#define CORE99_ADLER_START 0x14
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/* On Core99, nvram is either a sharp, a micron or an AMD flash */
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#define SM_FLASH_STATUS_DONE 0x80
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#define SM_FLASH_STATUS_ERR 0x38
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#define SM_FLASH_CMD_ERASE_CONFIRM 0xd0
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#define SM_FLASH_CMD_ERASE_SETUP 0x20
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#define SM_FLASH_CMD_RESET 0xff
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#define SM_FLASH_CMD_WRITE_SETUP 0x40
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#define SM_FLASH_CMD_CLEAR_STATUS 0x50
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#define SM_FLASH_CMD_READ_STATUS 0x70
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/* CHRP NVRAM header */
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struct chrp_header {
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u8 signature;
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u8 cksum;
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u16 len;
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char name[12];
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u8 data[];
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};
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struct core99_header {
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struct chrp_header hdr;
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u32 adler;
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u32 generation;
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u32 reserved[2];
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};
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/*
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* Read and write the non-volatile RAM on PowerMacs and CHRP machines.
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*/
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static int nvram_naddrs;
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static volatile unsigned char __iomem *nvram_data;
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static int is_core_99;
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static int core99_bank = 0;
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static int nvram_partitions[3];
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// XXX Turn that into a sem
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static DEFINE_RAW_SPINLOCK(nv_lock);
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static int (*core99_write_bank)(int bank, u8* datas);
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static int (*core99_erase_bank)(int bank);
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static char *nvram_image;
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static unsigned char core99_nvram_read_byte(int addr)
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{
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if (nvram_image == NULL)
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return 0xff;
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return nvram_image[addr];
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}
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static void core99_nvram_write_byte(int addr, unsigned char val)
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{
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if (nvram_image == NULL)
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return;
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nvram_image[addr] = val;
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}
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static ssize_t core99_nvram_read(char *buf, size_t count, loff_t *index)
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{
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int i;
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if (nvram_image == NULL)
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return -ENODEV;
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if (*index > NVRAM_SIZE)
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return 0;
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i = *index;
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if (i + count > NVRAM_SIZE)
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count = NVRAM_SIZE - i;
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memcpy(buf, &nvram_image[i], count);
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*index = i + count;
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return count;
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}
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static ssize_t core99_nvram_write(char *buf, size_t count, loff_t *index)
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{
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int i;
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if (nvram_image == NULL)
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return -ENODEV;
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if (*index > NVRAM_SIZE)
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return 0;
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i = *index;
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if (i + count > NVRAM_SIZE)
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count = NVRAM_SIZE - i;
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memcpy(&nvram_image[i], buf, count);
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*index = i + count;
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return count;
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}
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static ssize_t core99_nvram_size(void)
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{
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if (nvram_image == NULL)
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return -ENODEV;
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return NVRAM_SIZE;
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}
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#ifdef CONFIG_PPC32
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static volatile unsigned char __iomem *nvram_addr;
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static int nvram_mult;
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static ssize_t ppc32_nvram_size(void)
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{
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return NVRAM_SIZE;
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}
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static unsigned char direct_nvram_read_byte(int addr)
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{
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return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
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}
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static void direct_nvram_write_byte(int addr, unsigned char val)
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{
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out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
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}
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static unsigned char indirect_nvram_read_byte(int addr)
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{
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unsigned char val;
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unsigned long flags;
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raw_spin_lock_irqsave(&nv_lock, flags);
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out_8(nvram_addr, addr >> 5);
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val = in_8(&nvram_data[(addr & 0x1f) << 4]);
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raw_spin_unlock_irqrestore(&nv_lock, flags);
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return val;
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}
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static void indirect_nvram_write_byte(int addr, unsigned char val)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&nv_lock, flags);
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out_8(nvram_addr, addr >> 5);
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out_8(&nvram_data[(addr & 0x1f) << 4], val);
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raw_spin_unlock_irqrestore(&nv_lock, flags);
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}
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#ifdef CONFIG_ADB_PMU
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static void pmu_nvram_complete(struct adb_request *req)
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{
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if (req->arg)
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complete((struct completion *)req->arg);
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}
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static unsigned char pmu_nvram_read_byte(int addr)
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{
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struct adb_request req;
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DECLARE_COMPLETION_ONSTACK(req_complete);
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req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
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if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
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(addr >> 8) & 0xff, addr & 0xff))
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return 0xff;
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if (system_state == SYSTEM_RUNNING)
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wait_for_completion(&req_complete);
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while (!req.complete)
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pmu_poll();
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return req.reply[0];
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}
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static void pmu_nvram_write_byte(int addr, unsigned char val)
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{
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struct adb_request req;
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DECLARE_COMPLETION_ONSTACK(req_complete);
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req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
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if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
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(addr >> 8) & 0xff, addr & 0xff, val))
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return;
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if (system_state == SYSTEM_RUNNING)
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wait_for_completion(&req_complete);
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while (!req.complete)
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pmu_poll();
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}
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#endif /* CONFIG_ADB_PMU */
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#endif /* CONFIG_PPC32 */
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static u8 chrp_checksum(struct chrp_header* hdr)
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{
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u8 *ptr;
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u16 sum = hdr->signature;
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for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
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sum += *ptr;
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while (sum > 0xFF)
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sum = (sum & 0xFF) + (sum>>8);
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return sum;
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}
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static u32 core99_calc_adler(u8 *buffer)
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{
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int cnt;
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u32 low, high;
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buffer += CORE99_ADLER_START;
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low = 1;
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high = 0;
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for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
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if ((cnt % 5000) == 0) {
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high %= 65521UL;
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high %= 65521UL;
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}
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low += buffer[cnt];
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high += low;
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}
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low %= 65521UL;
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high %= 65521UL;
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return (high << 16) | low;
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}
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static u32 core99_check(u8* datas)
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{
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struct core99_header* hdr99 = (struct core99_header*)datas;
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if (hdr99->hdr.signature != CORE99_SIGNATURE) {
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DBG("Invalid signature\n");
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return 0;
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}
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if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
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DBG("Invalid checksum\n");
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return 0;
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}
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if (hdr99->adler != core99_calc_adler(datas)) {
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DBG("Invalid adler\n");
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return 0;
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}
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return hdr99->generation;
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}
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static int sm_erase_bank(int bank)
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{
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int stat;
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unsigned long timeout;
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u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
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out_8(base, SM_FLASH_CMD_ERASE_SETUP);
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out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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printk(KERN_ERR "nvram: Sharp/Micron flash erase timeout !\n");
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break;
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}
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out_8(base, SM_FLASH_CMD_READ_STATUS);
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stat = in_8(base);
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} while (!(stat & SM_FLASH_STATUS_DONE));
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out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
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out_8(base, SM_FLASH_CMD_RESET);
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if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
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printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
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return -ENXIO;
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}
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return 0;
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}
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static int sm_write_bank(int bank, u8* datas)
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{
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int i, stat = 0;
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unsigned long timeout;
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u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
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for (i=0; i<NVRAM_SIZE; i++) {
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out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
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udelay(1);
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out_8(base+i, datas[i]);
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
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break;
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}
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out_8(base, SM_FLASH_CMD_READ_STATUS);
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stat = in_8(base);
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} while (!(stat & SM_FLASH_STATUS_DONE));
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if (!(stat & SM_FLASH_STATUS_DONE))
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break;
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}
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out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
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out_8(base, SM_FLASH_CMD_RESET);
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if (memcmp(base, datas, NVRAM_SIZE)) {
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printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
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return -ENXIO;
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}
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return 0;
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}
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static int amd_erase_bank(int bank)
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{
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int stat = 0;
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unsigned long timeout;
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u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: AMD Erasing bank %d...\n", bank);
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/* Unlock 1 */
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out_8(base+0x555, 0xaa);
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udelay(1);
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/* Unlock 2 */
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out_8(base+0x2aa, 0x55);
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udelay(1);
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/* Sector-Erase */
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out_8(base+0x555, 0x80);
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udelay(1);
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out_8(base+0x555, 0xaa);
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udelay(1);
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out_8(base+0x2aa, 0x55);
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udelay(1);
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out_8(base, 0x30);
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udelay(1);
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
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break;
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}
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stat = in_8(base) ^ in_8(base);
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} while (stat != 0);
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/* Reset */
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out_8(base, 0xf0);
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udelay(1);
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if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
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printk(KERN_ERR "nvram: AMD flash erase failed !\n");
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return -ENXIO;
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}
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return 0;
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}
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static int amd_write_bank(int bank, u8* datas)
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{
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int i, stat = 0;
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unsigned long timeout;
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u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: AMD Writing bank %d...\n", bank);
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for (i=0; i<NVRAM_SIZE; i++) {
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/* Unlock 1 */
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out_8(base+0x555, 0xaa);
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udelay(1);
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/* Unlock 2 */
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out_8(base+0x2aa, 0x55);
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udelay(1);
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/* Write single word */
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out_8(base+0x555, 0xa0);
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udelay(1);
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out_8(base+i, datas[i]);
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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printk(KERN_ERR "nvram: AMD flash write timeout !\n");
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break;
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}
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stat = in_8(base) ^ in_8(base);
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} while (stat != 0);
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if (stat != 0)
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break;
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}
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/* Reset */
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out_8(base, 0xf0);
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udelay(1);
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if (memcmp(base, datas, NVRAM_SIZE)) {
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printk(KERN_ERR "nvram: AMD flash write failed !\n");
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return -ENXIO;
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}
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return 0;
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}
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static void __init lookup_partitions(void)
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{
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u8 buffer[17];
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int i, offset;
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struct chrp_header* hdr;
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|
if (pmac_newworld) {
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nvram_partitions[pmac_nvram_OF] = -1;
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nvram_partitions[pmac_nvram_XPRAM] = -1;
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nvram_partitions[pmac_nvram_NR] = -1;
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hdr = (struct chrp_header *)buffer;
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offset = 0;
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buffer[16] = 0;
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do {
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for (i=0;i<16;i++)
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buffer[i] = ppc_md.nvram_read_val(offset+i);
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if (!strcmp(hdr->name, "common"))
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nvram_partitions[pmac_nvram_OF] = offset + 0x10;
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if (!strcmp(hdr->name, "APL,MacOS75")) {
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nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
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nvram_partitions[pmac_nvram_NR] = offset + 0x110;
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}
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offset += (hdr->len * 0x10);
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} while(offset < NVRAM_SIZE);
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} else {
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nvram_partitions[pmac_nvram_OF] = 0x1800;
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nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
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nvram_partitions[pmac_nvram_NR] = 0x1400;
|
}
|
DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
|
DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
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DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
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}
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static void core99_nvram_sync(void)
|
{
|
struct core99_header* hdr99;
|
unsigned long flags;
|
|
if (!is_core_99 || !nvram_data || !nvram_image)
|
return;
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|
raw_spin_lock_irqsave(&nv_lock, flags);
|
if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
|
NVRAM_SIZE))
|
goto bail;
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|
DBG("Updating nvram...\n");
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|
hdr99 = (struct core99_header*)nvram_image;
|
hdr99->generation++;
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hdr99->hdr.signature = CORE99_SIGNATURE;
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hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
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hdr99->adler = core99_calc_adler(nvram_image);
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core99_bank = core99_bank ? 0 : 1;
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if (core99_erase_bank)
|
if (core99_erase_bank(core99_bank)) {
|
printk("nvram: Error erasing bank %d\n", core99_bank);
|
goto bail;
|
}
|
if (core99_write_bank)
|
if (core99_write_bank(core99_bank, nvram_image))
|
printk("nvram: Error writing bank %d\n", core99_bank);
|
bail:
|
raw_spin_unlock_irqrestore(&nv_lock, flags);
|
|
#ifdef DEBUG
|
mdelay(2000);
|
#endif
|
}
|
|
static int __init core99_nvram_setup(struct device_node *dp, unsigned long addr)
|
{
|
int i;
|
u32 gen_bank0, gen_bank1;
|
|
if (nvram_naddrs < 1) {
|
printk(KERN_ERR "nvram: no address\n");
|
return -EINVAL;
|
}
|
nvram_image = memblock_alloc(NVRAM_SIZE, SMP_CACHE_BYTES);
|
if (!nvram_image)
|
panic("%s: Failed to allocate %u bytes\n", __func__,
|
NVRAM_SIZE);
|
nvram_data = ioremap(addr, NVRAM_SIZE*2);
|
nvram_naddrs = 1; /* Make sure we get the correct case */
|
|
DBG("nvram: Checking bank 0...\n");
|
|
gen_bank0 = core99_check((u8 *)nvram_data);
|
gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
|
core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
|
|
DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
|
DBG("nvram: Active bank is: %d\n", core99_bank);
|
|
for (i=0; i<NVRAM_SIZE; i++)
|
nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
|
|
ppc_md.nvram_read_val = core99_nvram_read_byte;
|
ppc_md.nvram_write_val = core99_nvram_write_byte;
|
ppc_md.nvram_read = core99_nvram_read;
|
ppc_md.nvram_write = core99_nvram_write;
|
ppc_md.nvram_size = core99_nvram_size;
|
ppc_md.nvram_sync = core99_nvram_sync;
|
ppc_md.machine_shutdown = core99_nvram_sync;
|
/*
|
* Maybe we could be smarter here though making an exclusive list
|
* of known flash chips is a bit nasty as older OF didn't provide us
|
* with a useful "compatible" entry. A solution would be to really
|
* identify the chip using flash id commands and base ourselves on
|
* a list of known chips IDs
|
*/
|
if (of_device_is_compatible(dp, "amd-0137")) {
|
core99_erase_bank = amd_erase_bank;
|
core99_write_bank = amd_write_bank;
|
} else {
|
core99_erase_bank = sm_erase_bank;
|
core99_write_bank = sm_write_bank;
|
}
|
return 0;
|
}
|
|
int __init pmac_nvram_init(void)
|
{
|
struct device_node *dp;
|
struct resource r1, r2;
|
unsigned int s1 = 0, s2 = 0;
|
int err = 0;
|
|
nvram_naddrs = 0;
|
|
dp = of_find_node_by_name(NULL, "nvram");
|
if (dp == NULL) {
|
printk(KERN_ERR "Can't find NVRAM device\n");
|
return -ENODEV;
|
}
|
|
/* Try to obtain an address */
|
if (of_address_to_resource(dp, 0, &r1) == 0) {
|
nvram_naddrs = 1;
|
s1 = resource_size(&r1);
|
if (of_address_to_resource(dp, 1, &r2) == 0) {
|
nvram_naddrs = 2;
|
s2 = resource_size(&r2);
|
}
|
}
|
|
is_core_99 = of_device_is_compatible(dp, "nvram,flash");
|
if (is_core_99) {
|
err = core99_nvram_setup(dp, r1.start);
|
goto bail;
|
}
|
|
#ifdef CONFIG_PPC32
|
if (machine_is(chrp) && nvram_naddrs == 1) {
|
nvram_data = ioremap(r1.start, s1);
|
nvram_mult = 1;
|
ppc_md.nvram_read_val = direct_nvram_read_byte;
|
ppc_md.nvram_write_val = direct_nvram_write_byte;
|
ppc_md.nvram_size = ppc32_nvram_size;
|
} else if (nvram_naddrs == 1) {
|
nvram_data = ioremap(r1.start, s1);
|
nvram_mult = (s1 + NVRAM_SIZE - 1) / NVRAM_SIZE;
|
ppc_md.nvram_read_val = direct_nvram_read_byte;
|
ppc_md.nvram_write_val = direct_nvram_write_byte;
|
ppc_md.nvram_size = ppc32_nvram_size;
|
} else if (nvram_naddrs == 2) {
|
nvram_addr = ioremap(r1.start, s1);
|
nvram_data = ioremap(r2.start, s2);
|
ppc_md.nvram_read_val = indirect_nvram_read_byte;
|
ppc_md.nvram_write_val = indirect_nvram_write_byte;
|
ppc_md.nvram_size = ppc32_nvram_size;
|
} else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
|
#ifdef CONFIG_ADB_PMU
|
nvram_naddrs = -1;
|
ppc_md.nvram_read_val = pmu_nvram_read_byte;
|
ppc_md.nvram_write_val = pmu_nvram_write_byte;
|
ppc_md.nvram_size = ppc32_nvram_size;
|
#endif /* CONFIG_ADB_PMU */
|
} else {
|
printk(KERN_ERR "Incompatible type of NVRAM\n");
|
err = -ENXIO;
|
}
|
#endif /* CONFIG_PPC32 */
|
bail:
|
of_node_put(dp);
|
if (err == 0)
|
lookup_partitions();
|
return err;
|
}
|
|
int pmac_get_partition(int partition)
|
{
|
return nvram_partitions[partition];
|
}
|
|
u8 pmac_xpram_read(int xpaddr)
|
{
|
int offset = pmac_get_partition(pmac_nvram_XPRAM);
|
|
if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
|
return 0xff;
|
|
return ppc_md.nvram_read_val(xpaddr + offset);
|
}
|
|
void pmac_xpram_write(int xpaddr, u8 data)
|
{
|
int offset = pmac_get_partition(pmac_nvram_XPRAM);
|
|
if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
|
return;
|
|
ppc_md.nvram_write_val(xpaddr + offset, data);
|
}
|
|
EXPORT_SYMBOL(pmac_get_partition);
|
EXPORT_SYMBOL(pmac_xpram_read);
|
EXPORT_SYMBOL(pmac_xpram_write);
|
