// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Author: Andy Fleming <afleming@freescale.com>
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* Kumar Gala <galak@kernel.crashing.org>
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*
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* Copyright 2006-2008, 2011-2012, 2015 Freescale Semiconductor Inc.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/sched/hotplug.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/kexec.h>
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#include <linux/highmem.h>
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#include <linux/cpu.h>
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#include <linux/fsl/guts.h>
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#include <linux/pgtable.h>
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#include <asm/machdep.h>
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#include <asm/page.h>
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#include <asm/mpic.h>
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#include <asm/cacheflush.h>
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#include <asm/dbell.h>
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#include <asm/code-patching.h>
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#include <asm/cputhreads.h>
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#include <asm/fsl_pm.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/mpic.h>
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#include "smp.h"
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struct epapr_spin_table {
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u32 addr_h;
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u32 addr_l;
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u32 r3_h;
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u32 r3_l;
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u32 reserved;
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u32 pir;
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};
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static u64 timebase;
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static int tb_req;
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static int tb_valid;
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static void mpc85xx_give_timebase(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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hard_irq_disable();
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while (!tb_req)
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barrier();
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tb_req = 0;
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qoriq_pm_ops->freeze_time_base(true);
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#ifdef CONFIG_PPC64
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/*
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* e5500/e6500 have a workaround for erratum A-006958 in place
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* that will reread the timebase until TBL is non-zero.
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* That would be a bad thing when the timebase is frozen.
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*
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* Thus, we read it manually, and instead of checking that
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* TBL is non-zero, we ensure that TB does not change. We don't
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* do that for the main mftb implementation, because it requires
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* a scratch register
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*/
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{
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u64 prev;
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asm volatile("mfspr %0, %1" : "=r" (timebase) :
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"i" (SPRN_TBRL));
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do {
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prev = timebase;
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asm volatile("mfspr %0, %1" : "=r" (timebase) :
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"i" (SPRN_TBRL));
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} while (prev != timebase);
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}
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#else
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timebase = get_tb();
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#endif
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mb();
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tb_valid = 1;
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while (tb_valid)
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barrier();
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qoriq_pm_ops->freeze_time_base(false);
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local_irq_restore(flags);
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}
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static void mpc85xx_take_timebase(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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hard_irq_disable();
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tb_req = 1;
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while (!tb_valid)
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barrier();
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set_tb(timebase >> 32, timebase & 0xffffffff);
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isync();
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tb_valid = 0;
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local_irq_restore(flags);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static void smp_85xx_cpu_offline_self(void)
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{
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unsigned int cpu = smp_processor_id();
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local_irq_disable();
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hard_irq_disable();
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/* mask all irqs to prevent cpu wakeup */
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qoriq_pm_ops->irq_mask(cpu);
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idle_task_exit();
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mtspr(SPRN_TCR, 0);
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mtspr(SPRN_TSR, mfspr(SPRN_TSR));
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generic_set_cpu_dead(cpu);
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cur_cpu_spec->cpu_down_flush();
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qoriq_pm_ops->cpu_die(cpu);
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while (1)
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;
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}
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static void qoriq_cpu_kill(unsigned int cpu)
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{
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int i;
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for (i = 0; i < 500; i++) {
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if (is_cpu_dead(cpu)) {
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#ifdef CONFIG_PPC64
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paca_ptrs[cpu]->cpu_start = 0;
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#endif
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return;
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}
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msleep(20);
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}
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pr_err("CPU%d didn't die...\n", cpu);
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}
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#endif
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/*
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* To keep it compatible with old boot program which uses
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* cache-inhibit spin table, we need to flush the cache
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* before accessing spin table to invalidate any staled data.
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* We also need to flush the cache after writing to spin
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* table to push data out.
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*/
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static inline void flush_spin_table(void *spin_table)
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{
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flush_dcache_range((ulong)spin_table,
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(ulong)spin_table + sizeof(struct epapr_spin_table));
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}
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static inline u32 read_spin_table_addr_l(void *spin_table)
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{
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flush_dcache_range((ulong)spin_table,
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(ulong)spin_table + sizeof(struct epapr_spin_table));
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return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l);
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}
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#ifdef CONFIG_PPC64
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static void wake_hw_thread(void *info)
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{
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void fsl_secondary_thread_init(void);
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unsigned long inia;
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int cpu = *(const int *)info;
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inia = *(unsigned long *)fsl_secondary_thread_init;
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book3e_start_thread(cpu_thread_in_core(cpu), inia);
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}
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#endif
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static int smp_85xx_start_cpu(int cpu)
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{
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int ret = 0;
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struct device_node *np;
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const u64 *cpu_rel_addr;
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unsigned long flags;
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int ioremappable;
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int hw_cpu = get_hard_smp_processor_id(cpu);
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struct epapr_spin_table __iomem *spin_table;
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np = of_get_cpu_node(cpu, NULL);
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cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);
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if (!cpu_rel_addr) {
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pr_err("No cpu-release-addr for cpu %d\n", cpu);
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return -ENOENT;
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}
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/*
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* A secondary core could be in a spinloop in the bootpage
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* (0xfffff000), somewhere in highmem, or somewhere in lowmem.
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* The bootpage and highmem can be accessed via ioremap(), but
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* we need to directly access the spinloop if its in lowmem.
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*/
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ioremappable = *cpu_rel_addr > virt_to_phys(high_memory);
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/* Map the spin table */
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if (ioremappable)
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spin_table = ioremap_coherent(*cpu_rel_addr,
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sizeof(struct epapr_spin_table));
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else
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spin_table = phys_to_virt(*cpu_rel_addr);
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local_irq_save(flags);
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hard_irq_disable();
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if (qoriq_pm_ops && qoriq_pm_ops->cpu_up_prepare)
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qoriq_pm_ops->cpu_up_prepare(cpu);
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/* if cpu is not spinning, reset it */
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if (read_spin_table_addr_l(spin_table) != 1) {
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/*
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* We don't set the BPTR register here since it already points
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* to the boot page properly.
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*/
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mpic_reset_core(cpu);
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/*
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* wait until core is ready...
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* We need to invalidate the stale data, in case the boot
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* loader uses a cache-inhibited spin table.
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*/
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if (!spin_event_timeout(
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read_spin_table_addr_l(spin_table) == 1,
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10000, 100)) {
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pr_err("timeout waiting for cpu %d to reset\n",
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hw_cpu);
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ret = -EAGAIN;
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goto err;
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}
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}
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flush_spin_table(spin_table);
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out_be32(&spin_table->pir, hw_cpu);
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#ifdef CONFIG_PPC64
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out_be64((u64 *)(&spin_table->addr_h),
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__pa(ppc_function_entry(generic_secondary_smp_init)));
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#else
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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/*
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* We need also to write addr_h to spin table for systems
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* in which their physical memory start address was configured
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* to above 4G, otherwise the secondary core can not get
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* correct entry to start from.
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*/
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out_be32(&spin_table->addr_h, __pa(__early_start) >> 32);
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#endif
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out_be32(&spin_table->addr_l, __pa(__early_start));
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#endif
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flush_spin_table(spin_table);
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err:
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local_irq_restore(flags);
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if (ioremappable)
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iounmap(spin_table);
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return ret;
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}
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static int smp_85xx_kick_cpu(int nr)
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{
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int ret = 0;
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#ifdef CONFIG_PPC64
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int primary = nr;
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#endif
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WARN_ON(nr < 0 || nr >= num_possible_cpus());
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pr_debug("kick CPU #%d\n", nr);
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#ifdef CONFIG_PPC64
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if (threads_per_core == 2) {
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if (WARN_ON_ONCE(!cpu_has_feature(CPU_FTR_SMT)))
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return -ENOENT;
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booting_thread_hwid = cpu_thread_in_core(nr);
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primary = cpu_first_thread_sibling(nr);
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if (qoriq_pm_ops && qoriq_pm_ops->cpu_up_prepare)
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qoriq_pm_ops->cpu_up_prepare(nr);
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/*
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* If either thread in the core is online, use it to start
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* the other.
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*/
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if (cpu_online(primary)) {
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smp_call_function_single(primary,
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wake_hw_thread, &nr, 1);
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goto done;
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} else if (cpu_online(primary + 1)) {
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smp_call_function_single(primary + 1,
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wake_hw_thread, &nr, 1);
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goto done;
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}
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/*
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* If getting here, it means both threads in the core are
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* offline. So start the primary thread, then it will start
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* the thread specified in booting_thread_hwid, the one
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* corresponding to nr.
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*/
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} else if (threads_per_core == 1) {
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/*
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* If one core has only one thread, set booting_thread_hwid to
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* an invalid value.
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*/
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booting_thread_hwid = INVALID_THREAD_HWID;
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} else if (threads_per_core > 2) {
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pr_err("Do not support more than 2 threads per CPU.");
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return -EINVAL;
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}
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ret = smp_85xx_start_cpu(primary);
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if (ret)
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return ret;
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done:
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paca_ptrs[nr]->cpu_start = 1;
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generic_set_cpu_up(nr);
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return ret;
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#else
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ret = smp_85xx_start_cpu(nr);
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if (ret)
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return ret;
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generic_set_cpu_up(nr);
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return ret;
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#endif
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}
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struct smp_ops_t smp_85xx_ops = {
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.cause_nmi_ipi = NULL,
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.kick_cpu = smp_85xx_kick_cpu,
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.cpu_bootable = smp_generic_cpu_bootable,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_disable = generic_cpu_disable,
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.cpu_die = generic_cpu_die,
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#endif
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#if defined(CONFIG_KEXEC_CORE) && !defined(CONFIG_PPC64)
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.give_timebase = smp_generic_give_timebase,
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.take_timebase = smp_generic_take_timebase,
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#endif
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};
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#ifdef CONFIG_KEXEC_CORE
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#ifdef CONFIG_PPC32
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atomic_t kexec_down_cpus = ATOMIC_INIT(0);
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void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
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{
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local_irq_disable();
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if (secondary) {
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cur_cpu_spec->cpu_down_flush();
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atomic_inc(&kexec_down_cpus);
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/* loop forever */
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while (1);
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}
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}
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static void mpc85xx_smp_kexec_down(void *arg)
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{
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if (ppc_md.kexec_cpu_down)
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ppc_md.kexec_cpu_down(0,1);
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}
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#else
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void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
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{
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int cpu = smp_processor_id();
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int sibling = cpu_last_thread_sibling(cpu);
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bool notified = false;
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int disable_cpu;
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int disable_threadbit = 0;
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long start = mftb();
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long now;
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local_irq_disable();
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hard_irq_disable();
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mpic_teardown_this_cpu(secondary);
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if (cpu == crashing_cpu && cpu_thread_in_core(cpu) != 0) {
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/*
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* We enter the crash kernel on whatever cpu crashed,
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* even if it's a secondary thread. If that's the case,
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* disable the corresponding primary thread.
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*/
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disable_threadbit = 1;
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disable_cpu = cpu_first_thread_sibling(cpu);
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} else if (sibling != crashing_cpu &&
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cpu_thread_in_core(cpu) == 0 &&
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cpu_thread_in_core(sibling) != 0) {
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disable_threadbit = 2;
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disable_cpu = sibling;
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}
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if (disable_threadbit) {
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while (paca_ptrs[disable_cpu]->kexec_state < KEXEC_STATE_REAL_MODE) {
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barrier();
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now = mftb();
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if (!notified && now - start > 1000000) {
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pr_info("%s/%d: waiting for cpu %d to enter KEXEC_STATE_REAL_MODE (%d)\n",
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__func__, smp_processor_id(),
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disable_cpu,
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paca_ptrs[disable_cpu]->kexec_state);
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notified = true;
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}
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}
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if (notified) {
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pr_info("%s: cpu %d done waiting\n",
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__func__, disable_cpu);
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}
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mtspr(SPRN_TENC, disable_threadbit);
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while (mfspr(SPRN_TENSR) & disable_threadbit)
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cpu_relax();
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}
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}
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#endif
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static void mpc85xx_smp_machine_kexec(struct kimage *image)
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{
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#ifdef CONFIG_PPC32
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int timeout = INT_MAX;
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int i, num_cpus = num_present_cpus();
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if (image->type == KEXEC_TYPE_DEFAULT)
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smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
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while ( (atomic_read(&kexec_down_cpus) != (num_cpus - 1)) &&
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( timeout > 0 ) )
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{
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timeout--;
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}
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if ( !timeout )
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printk(KERN_ERR "Unable to bring down secondary cpu(s)");
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for_each_online_cpu(i)
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{
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if ( i == smp_processor_id() ) continue;
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mpic_reset_core(i);
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}
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#endif
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default_machine_kexec(image);
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}
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#endif /* CONFIG_KEXEC_CORE */
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static void smp_85xx_setup_cpu(int cpu_nr)
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{
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mpic_setup_this_cpu();
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}
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void __init mpc85xx_smp_init(void)
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{
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struct device_node *np;
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np = of_find_node_by_type(NULL, "open-pic");
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if (np) {
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smp_85xx_ops.probe = smp_mpic_probe;
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smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
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smp_85xx_ops.message_pass = smp_mpic_message_pass;
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} else
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smp_85xx_ops.setup_cpu = NULL;
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if (cpu_has_feature(CPU_FTR_DBELL)) {
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/*
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* If left NULL, .message_pass defaults to
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* smp_muxed_ipi_message_pass
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*/
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smp_85xx_ops.message_pass = NULL;
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smp_85xx_ops.cause_ipi = doorbell_global_ipi;
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smp_85xx_ops.probe = NULL;
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}
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#ifdef CONFIG_FSL_CORENET_RCPM
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/* Assign a value to qoriq_pm_ops on PPC_E500MC */
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fsl_rcpm_init();
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#else
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/* Assign a value to qoriq_pm_ops on !PPC_E500MC */
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mpc85xx_setup_pmc();
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#endif
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if (qoriq_pm_ops) {
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smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
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smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
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#ifdef CONFIG_HOTPLUG_CPU
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smp_85xx_ops.cpu_offline_self = smp_85xx_cpu_offline_self;
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smp_85xx_ops.cpu_die = qoriq_cpu_kill;
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#endif
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}
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smp_ops = &smp_85xx_ops;
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#ifdef CONFIG_KEXEC_CORE
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ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down;
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ppc_md.machine_kexec = mpc85xx_smp_machine_kexec;
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#endif
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}
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