/*
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* Copyright (C) 2019 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <asm/utils.h>
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#include <clk.h>
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#include <dm.h>
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#include <reset.h>
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#include <wdt.h>
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#define WDT_CR 0x00
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#define WDT_TORR 0x04
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#define WDT_CRR 0x0C
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#define WDT_EN_MASK 0x01
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#define WDT_MODE_MASK 0x02
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#define WDT_CRR_RESTART_VAL 0x76
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DECLARE_GLOBAL_DATA_PTR;
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struct rockchip_wdt_priv {
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void __iomem *base;
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struct clk clk;
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unsigned long rate;
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struct reset_ctl rst;
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};
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/*
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* Set the watchdog time interval.
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* Counter is 32 bit.
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*/
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static int rockchip_wdt_settimeout(u64 timeout,
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struct rockchip_wdt_priv *priv)
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{
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signed int i;
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/* calculate the timeout range value */
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i = log_2_n_round_up(timeout * priv->rate / 1000) - 16;
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if (i > 15)
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i = 15;
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if (i < 0)
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i = 0;
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writel((i | (i << 4)), priv->base + WDT_TORR);
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return 0;
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}
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static void rockchip_wdt_enable(struct rockchip_wdt_priv *priv)
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{
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u32 val = readl(priv->base + WDT_CR);
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/* Disable interrupt mode; always perform system reset. */
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val &= ~WDT_MODE_MASK;
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/* Enable watchdog. */
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val |= WDT_EN_MASK;
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writel(val, priv->base + WDT_CR);
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}
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static unsigned int rockchip_wdt_is_enabled(struct rockchip_wdt_priv *priv)
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{
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unsigned long val;
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val = readl(priv->base + WDT_CR);
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return val & WDT_EN_MASK;
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}
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static int rockchip_wdt_reset(struct udevice *dev)
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{
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struct rockchip_wdt_priv *priv = dev_get_priv(dev);
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if (rockchip_wdt_is_enabled(priv))
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/* restart the watchdog counter */
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writel(WDT_CRR_RESTART_VAL, priv->base + WDT_CRR);
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return 0;
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}
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static int rockchip_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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struct rockchip_wdt_priv *priv = dev_get_priv(dev);
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printf("Rockchip watchdog timeout: %lld sec\n", timeout / 1000);
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if (priv->rst.dev)
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reset_deassert(&priv->rst);
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rockchip_wdt_reset(dev);
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rockchip_wdt_settimeout(timeout, priv);
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rockchip_wdt_enable(priv);
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rockchip_wdt_reset(dev);
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return 0;
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}
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static int rockchip_wdt_stop(struct udevice *dev)
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{
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struct rockchip_wdt_priv *priv = dev_get_priv(dev);
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if (priv->rst.dev) {
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reset_assert(&priv->rst);
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reset_deassert(&priv->rst);
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}
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printf("Rockchip watchdog stop\n");
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return 0;
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}
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static const struct wdt_ops rockchip_wdt_ops = {
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.start = rockchip_wdt_start,
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.reset = rockchip_wdt_reset,
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.stop = rockchip_wdt_stop,
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};
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static int rockchip_wdt_ofdata_to_platdata(struct udevice *dev)
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{
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struct rockchip_wdt_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -ENOENT;
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return 0;
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}
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static int rockchip_wdt_probe(struct udevice *dev)
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{
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struct rockchip_wdt_priv *priv = dev_get_priv(dev);
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int ret;
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ret = reset_get_by_name(dev, "reset", &priv->rst);
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if (ret) {
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pr_err("reset_get_by_name(reset) failed: %d\n", ret);
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priv->rst.dev = NULL;
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}
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0)
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return ret;
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/* Need clk framework support */
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priv->rate = clk_get_rate(&priv->clk);
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if (priv->rate < 0)
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return -EINVAL;
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return 0;
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}
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static const struct udevice_id rockchip_wdt_ids[] = {
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{ .compatible = "snps,dw-wdt" },
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{}
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};
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U_BOOT_DRIVER(rockchip_wdt) = {
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.name = "rockchip_wdt",
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.id = UCLASS_WDT,
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.of_match = rockchip_wdt_ids,
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.probe = rockchip_wdt_probe,
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.priv_auto_alloc_size = sizeof(struct rockchip_wdt_priv),
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.ofdata_to_platdata = rockchip_wdt_ofdata_to_platdata,
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.ops = &rockchip_wdt_ops,
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};
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