/*
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* Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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*/
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#ifndef _RTL8152_ETH_H
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#define _RTL8152_ETH_H
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#define R8152_BASE_NAME "r8152"
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#define PLA_IDR 0xc000
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#define PLA_RCR 0xc010
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#define PLA_RMS 0xc016
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#define PLA_RXFIFO_CTRL0 0xc0a0
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#define PLA_RXFIFO_CTRL1 0xc0a4
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#define PLA_RXFIFO_CTRL2 0xc0a8
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#define PLA_DMY_REG0 0xc0b0
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#define PLA_FMC 0xc0b4
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#define PLA_CFG_WOL 0xc0b6
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#define PLA_TEREDO_CFG 0xc0bc
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#define PLA_MAR 0xcd00
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#define PLA_BACKUP 0xd000
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#define PAL_BDC_CR 0xd1a0
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#define PLA_TEREDO_TIMER 0xd2cc
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#define PLA_REALWOW_TIMER 0xd2e8
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#define PLA_LEDSEL 0xdd90
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#define PLA_LED_FEATURE 0xdd92
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#define PLA_PHYAR 0xde00
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#define PLA_BOOT_CTRL 0xe004
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#define PLA_GPHY_INTR_IMR 0xe022
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#define PLA_EEE_CR 0xe040
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#define PLA_EEEP_CR 0xe080
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#define PLA_MAC_PWR_CTRL 0xe0c0
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#define PLA_MAC_PWR_CTRL2 0xe0ca
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#define PLA_MAC_PWR_CTRL3 0xe0cc
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#define PLA_MAC_PWR_CTRL4 0xe0ce
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#define PLA_WDT6_CTRL 0xe428
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#define PLA_TCR0 0xe610
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#define PLA_TCR1 0xe612
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#define PLA_MTPS 0xe615
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#define PLA_TXFIFO_CTRL 0xe618
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#define PLA_RSTTALLY 0xe800
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#define BIST_CTRL 0xe810
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#define PLA_CR 0xe813
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#define PLA_CRWECR 0xe81c
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#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
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#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
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#define PLA_CONFIG5 0xe822
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#define PLA_PHY_PWR 0xe84c
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#define PLA_OOB_CTRL 0xe84f
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#define PLA_CPCR 0xe854
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#define PLA_MISC_0 0xe858
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#define PLA_MISC_1 0xe85a
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#define PLA_OCP_GPHY_BASE 0xe86c
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#define PLA_TALLYCNT 0xe890
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#define PLA_SFF_STS_7 0xe8de
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#define PLA_PHYSTATUS 0xe908
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#define PLA_BP_BA 0xfc26
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#define PLA_BP_0 0xfc28
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#define PLA_BP_1 0xfc2a
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#define PLA_BP_2 0xfc2c
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#define PLA_BP_3 0xfc2e
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#define PLA_BP_4 0xfc30
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#define PLA_BP_5 0xfc32
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#define PLA_BP_6 0xfc34
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#define PLA_BP_7 0xfc36
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#define PLA_BP_EN 0xfc38
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#define USB_USB2PHY 0xb41e
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#define USB_SSPHYLINK2 0xb428
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#define USB_U2P3_CTRL 0xb460
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#define USB_CSR_DUMMY1 0xb464
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#define USB_CSR_DUMMY2 0xb466
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#define USB_DEV_STAT 0xb808
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#define USB_CONNECT_TIMER 0xcbf8
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#define USB_BURST_SIZE 0xcfc0
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#define USB_USB_CTRL 0xd406
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#define USB_PHY_CTRL 0xd408
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#define USB_TX_AGG 0xd40a
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#define USB_RX_BUF_TH 0xd40c
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#define USB_USB_TIMER 0xd428
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#define USB_RX_EARLY_TIMEOUT 0xd42c
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#define USB_RX_EARLY_SIZE 0xd42e
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#define USB_PM_CTRL_STATUS 0xd432
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#define USB_TX_DMA 0xd434
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#define USB_TOLERANCE 0xd490
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#define USB_LPM_CTRL 0xd41a
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#define USB_UPS_CTRL 0xd800
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#define USB_MISC_0 0xd81a
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#define USB_POWER_CUT 0xd80a
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#define USB_AFE_CTRL2 0xd824
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#define USB_WDT11_CTRL 0xe43c
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#define USB_BP_BA 0xfc26
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#define USB_BP_0 0xfc28
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#define USB_BP_1 0xfc2a
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#define USB_BP_2 0xfc2c
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#define USB_BP_3 0xfc2e
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#define USB_BP_4 0xfc30
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#define USB_BP_5 0xfc32
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#define USB_BP_6 0xfc34
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#define USB_BP_7 0xfc36
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#define USB_BP_EN 0xfc38
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/* OCP Registers */
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#define OCP_ALDPS_CONFIG 0x2010
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#define OCP_EEE_CONFIG1 0x2080
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#define OCP_EEE_CONFIG2 0x2092
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#define OCP_EEE_CONFIG3 0x2094
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#define OCP_BASE_MII 0xa400
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#define OCP_EEE_AR 0xa41a
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#define OCP_EEE_DATA 0xa41c
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#define OCP_PHY_STATUS 0xa420
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#define OCP_POWER_CFG 0xa430
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#define OCP_EEE_CFG 0xa432
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#define OCP_SRAM_ADDR 0xa436
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#define OCP_SRAM_DATA 0xa438
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#define OCP_DOWN_SPEED 0xa442
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#define OCP_EEE_ABLE 0xa5c4
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#define OCP_EEE_ADV 0xa5d0
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#define OCP_EEE_LPABLE 0xa5d2
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#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
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#define OCP_ADC_CFG 0xbc06
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/* SRAM Register */
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#define SRAM_LPF_CFG 0x8012
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#define SRAM_10M_AMP1 0x8080
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#define SRAM_10M_AMP2 0x8082
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#define SRAM_IMPEDANCE 0x8084
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/* PLA_RCR */
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#define RCR_AAP 0x00000001
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#define RCR_APM 0x00000002
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#define RCR_AM 0x00000004
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#define RCR_AB 0x00000008
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#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
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/* PLA_RXFIFO_CTRL0 */
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#define RXFIFO_THR1_NORMAL 0x00080002
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#define RXFIFO_THR1_OOB 0x01800003
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/* PLA_RXFIFO_CTRL1 */
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#define RXFIFO_THR2_FULL 0x00000060
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#define RXFIFO_THR2_HIGH 0x00000038
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#define RXFIFO_THR2_OOB 0x0000004a
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#define RXFIFO_THR2_NORMAL 0x00a0
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/* PLA_RXFIFO_CTRL2 */
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#define RXFIFO_THR3_FULL 0x00000078
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#define RXFIFO_THR3_HIGH 0x00000048
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#define RXFIFO_THR3_OOB 0x0000005a
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#define RXFIFO_THR3_NORMAL 0x0110
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/* PLA_TXFIFO_CTRL */
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#define TXFIFO_THR_NORMAL 0x00400008
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#define TXFIFO_THR_NORMAL2 0x01000008
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/* PLA_DMY_REG0 */
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#define ECM_ALDPS 0x0002
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/* PLA_FMC */
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#define FMC_FCR_MCU_EN 0x0001
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/* PLA_EEEP_CR */
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#define EEEP_CR_EEEP_TX 0x0002
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/* PLA_WDT6_CTRL */
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#define WDT6_SET_MODE 0x0010
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/* PLA_TCR0 */
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#define TCR0_TX_EMPTY 0x0800
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#define TCR0_AUTO_FIFO 0x0080
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/* PLA_TCR1 */
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#define VERSION_MASK 0x7cf0
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/* PLA_MTPS */
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#define MTPS_JUMBO (12 * 1024 / 64)
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#define MTPS_DEFAULT (6 * 1024 / 64)
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/* PLA_RSTTALLY */
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#define TALLY_RESET 0x0001
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/* PLA_CR */
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#define PLA_CR_RST 0x10
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#define PLA_CR_RE 0x08
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#define PLA_CR_TE 0x04
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/* PLA_BIST_CTRL */
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#define BIST_CTRL_SW_RESET (0x10 << 24)
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/* PLA_CRWECR */
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#define CRWECR_NORAML 0x00
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#define CRWECR_CONFIG 0xc0
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/* PLA_OOB_CTRL */
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#define NOW_IS_OOB 0x80
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#define TXFIFO_EMPTY 0x20
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#define RXFIFO_EMPTY 0x10
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#define LINK_LIST_READY 0x02
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#define DIS_MCU_CLROOB 0x01
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#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
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/* PLA_PHY_PWR */
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#define PLA_PHY_PWR_LLR (LINK_LIST_READY << 24)
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#define PLA_PHY_PWR_TXEMP (TXFIFO_EMPTY << 24)
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/* PLA_MISC_1 */
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#define RXDY_GATED_EN 0x0008
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/* PLA_SFF_STS_7 */
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#define RE_INIT_LL 0x8000
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#define MCU_BORW_EN 0x4000
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/* PLA_CPCR */
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#define CPCR_RX_VLAN 0x0040
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/* PLA_CFG_WOL */
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#define MAGIC_EN 0x0001
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/* PLA_TEREDO_CFG */
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#define TEREDO_SEL 0x8000
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#define TEREDO_WAKE_MASK 0x7f00
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#define TEREDO_RS_EVENT_MASK 0x00fe
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#define OOB_TEREDO_EN 0x0001
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/* PAL_BDC_CR */
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#define ALDPS_PROXY_MODE 0x0001
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/* PLA_CONFIG34 */
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#define LINK_ON_WAKE_EN 0x0010
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#define LINK_OFF_WAKE_EN 0x0008
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/* PLA_CONFIG5 */
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#define BWF_EN 0x0040
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#define MWF_EN 0x0020
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#define UWF_EN 0x0010
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#define LAN_WAKE_EN 0x0002
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/* PLA_LED_FEATURE */
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#define LED_MODE_MASK 0x0700
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/* PLA_PHY_PWR */
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#define TX_10M_IDLE_EN 0x0080
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#define PFM_PWM_SWITCH 0x0040
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/* PLA_MAC_PWR_CTRL */
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#define D3_CLK_GATED_EN 0x00004000
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#define MCU_CLK_RATIO 0x07010f07
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#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
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#define ALDPS_SPDWN_RATIO 0x0f87
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/* PLA_MAC_PWR_CTRL2 */
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#define EEE_SPDWN_RATIO 0x8007
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/* PLA_MAC_PWR_CTRL3 */
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#define PKT_AVAIL_SPDWN_EN 0x0100
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#define SUSPEND_SPDWN_EN 0x0004
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#define U1U2_SPDWN_EN 0x0002
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#define L1_SPDWN_EN 0x0001
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/* PLA_MAC_PWR_CTRL4 */
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#define PWRSAVE_SPDWN_EN 0x1000
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#define RXDV_SPDWN_EN 0x0800
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#define TX10MIDLE_EN 0x0100
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#define TP100_SPDWN_EN 0x0020
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#define TP500_SPDWN_EN 0x0010
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#define TP1000_SPDWN_EN 0x0008
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#define EEE_SPDWN_EN 0x0001
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/* PLA_GPHY_INTR_IMR */
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#define GPHY_STS_MSK 0x0001
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#define SPEED_DOWN_MSK 0x0002
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#define SPDWN_RXDV_MSK 0x0004
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#define SPDWN_LINKCHG_MSK 0x0008
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/* PLA_PHYAR */
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#define PHYAR_FLAG 0x80000000
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/* PLA_EEE_CR */
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#define EEE_RX_EN 0x0001
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#define EEE_TX_EN 0x0002
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/* PLA_BOOT_CTRL */
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#define AUTOLOAD_DONE 0x0002
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/* USB_USB2PHY */
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#define USB2PHY_SUSPEND 0x0001
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#define USB2PHY_L1 0x0002
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/* USB_SSPHYLINK2 */
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#define pwd_dn_scale_mask 0x3ffe
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#define pwd_dn_scale(x) ((x) << 1)
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/* USB_CSR_DUMMY1 */
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#define DYNAMIC_BURST 0x0001
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/* USB_CSR_DUMMY2 */
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#define EP4_FULL_FC 0x0001
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/* USB_DEV_STAT */
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#define STAT_SPEED_MASK 0x0006
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#define STAT_SPEED_HIGH 0x0000
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#define STAT_SPEED_FULL 0x0002
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/* USB_TX_AGG */
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#define TX_AGG_MAX_THRESHOLD 0x03
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/* USB_RX_BUF_TH */
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#define RX_THR_SUPPER 0x0c350180
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#define RX_THR_HIGH 0x7a120180
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#define RX_THR_SLOW 0xffff0180
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/* USB_TX_DMA */
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#define TEST_MODE_DISABLE 0x00000001
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#define TX_SIZE_ADJUST1 0x00000100
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/* USB_UPS_CTRL */
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#define POWER_CUT 0x0100
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/* USB_PM_CTRL_STATUS */
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#define RESUME_INDICATE 0x0001
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/* USB_USB_CTRL */
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#define RX_AGG_DISABLE 0x0010
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#define RX_ZERO_EN 0x0080
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/* USB_U2P3_CTRL */
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#define U2P3_ENABLE 0x0001
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/* USB_POWER_CUT */
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#define PWR_EN 0x0001
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#define PHASE2_EN 0x0008
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/* USB_MISC_0 */
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#define PCUT_STATUS 0x0001
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/* USB_RX_EARLY_TIMEOUT */
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#define COALESCE_SUPER 85000U
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#define COALESCE_HIGH 250000U
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#define COALESCE_SLOW 524280U
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/* USB_WDT11_CTRL */
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#define TIMER11_EN 0x0001
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/* USB_LPM_CTRL */
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/* bit 4 ~ 5: fifo empty boundary */
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#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
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/* bit 2 ~ 3: LMP timer */
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#define LPM_TIMER_MASK 0x0c
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#define LPM_TIMER_500MS 0x04 /* 500 ms */
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#define LPM_TIMER_500US 0x0c /* 500 us */
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#define ROK_EXIT_LPM 0x02
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/* USB_AFE_CTRL2 */
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#define SEN_VAL_MASK 0xf800
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#define SEN_VAL_NORMAL 0xa000
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#define SEL_RXIDLE 0x0100
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/* OCP_ALDPS_CONFIG */
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#define ENPWRSAVE 0x8000
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#define ENPDNPS 0x0200
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#define LINKENA 0x0100
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#define DIS_SDSAVE 0x0010
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/* OCP_PHY_STATUS */
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#define PHY_STAT_MASK 0x0007
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#define PHY_STAT_LAN_ON 3
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#define PHY_STAT_PWRDN 5
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/* OCP_POWER_CFG */
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#define EEE_CLKDIV_EN 0x8000
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#define EN_ALDPS 0x0004
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#define EN_10M_PLLOFF 0x0001
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/* OCP_EEE_CONFIG1 */
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#define RG_TXLPI_MSK_HFDUP 0x8000
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#define RG_MATCLR_EN 0x4000
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#define EEE_10_CAP 0x2000
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#define EEE_NWAY_EN 0x1000
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#define TX_QUIET_EN 0x0200
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#define RX_QUIET_EN 0x0100
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#define sd_rise_time_mask 0x0070
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#define sd_rise_time(x) (min((x), 7) << 4) /* bit 4 ~ 6 */
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#define RG_RXLPI_MSK_HFDUP 0x0008
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#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
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/* OCP_EEE_CONFIG2 */
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#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
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#define RG_DACQUIET_EN 0x0400
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#define RG_LDVQUIET_EN 0x0200
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#define RG_CKRSEL 0x0020
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#define RG_EEEPRG_EN 0x0010
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/* OCP_EEE_CONFIG3 */
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#define fast_snr_mask 0xff80
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#define fast_snr(x) (min((x), 0x1ff) << 7) /* bit 7 ~ 15 */
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#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
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#define MSK_PH 0x0006 /* bit 0 ~ 3 */
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/* OCP_EEE_AR */
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/* bit[15:14] function */
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#define FUN_ADDR 0x0000
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#define FUN_DATA 0x4000
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/* bit[4:0] device addr */
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/* OCP_EEE_CFG */
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#define CTAP_SHORT_EN 0x0040
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#define EEE10_EN 0x0010
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/* OCP_DOWN_SPEED */
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#define EN_10M_BGOFF 0x0080
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/* OCP_PHY_STATE */
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#define TXDIS_STATE 0x01
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#define ABD_STATE 0x02
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/* OCP_ADC_CFG */
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#define CKADSEL_L 0x0100
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#define ADC_EN 0x0080
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#define EN_EMI_L 0x0040
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/* SRAM_LPF_CFG */
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#define LPF_AUTO_TUNE 0x8000
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/* SRAM_10M_AMP1 */
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#define GDAC_IB_UPALL 0x0008
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/* SRAM_10M_AMP2 */
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#define AMP_DN 0x0200
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/* SRAM_IMPEDANCE */
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#define RX_DRIVING_MASK 0x6000
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#define RTL8152_MAX_TX 4
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#define RTL8152_MAX_RX 10
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#define INTBUFSIZE 2
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#define CRC_SIZE 4
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#define TX_ALIGN 4
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#define RX_ALIGN 8
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#define INTR_LINK 0x0004
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#define RTL8152_REQT_READ 0xc0
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#define RTL8152_REQT_WRITE 0x40
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#define RTL8152_REQ_GET_REGS 0x05
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#define RTL8152_REQ_SET_REGS 0x05
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#define BYTE_EN_DWORD 0xff
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#define BYTE_EN_WORD 0x33
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#define BYTE_EN_BYTE 0x11
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#define BYTE_EN_SIX_BYTES 0x3f
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#define BYTE_EN_START_MASK 0x0f
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#define BYTE_EN_END_MASK 0xf0
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#define RTL8152_ETH_FRAME_LEN 1514
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#define RTL8152_AGG_BUF_SZ 2048
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#define RTL8152_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
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#define RTL8153_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
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#define RTL8152_TX_TIMEOUT (5 * HZ)
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#define MCU_TYPE_PLA 0x0100
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#define MCU_TYPE_USB 0x0000
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/* The forced speed, 10Mb, 100Mb, gigabit. */
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#define SPEED_10 10
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#define SPEED_100 100
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#define SPEED_1000 1000
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#define SPEED_UNKNOWN -1
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/* Duplex, half or full. */
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#define DUPLEX_HALF 0x00
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#define DUPLEX_FULL 0x01
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#define DUPLEX_UNKNOWN 0xff
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/* Enable or disable autonegotiation. */
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#define AUTONEG_DISABLE 0x00
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#define AUTONEG_ENABLE 0x01
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/* Generic MII registers. */
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#define MII_BMCR 0x00 /* Basic mode control register */
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#define MII_BMSR 0x01 /* Basic mode status register */
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#define MII_PHYSID1 0x02 /* PHYS ID 1 */
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#define MII_PHYSID2 0x03 /* PHYS ID 2 */
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#define MII_ADVERTISE 0x04 /* Advertisement control reg */
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#define MII_LPA 0x05 /* Link partner ability reg */
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#define MII_EXPANSION 0x06 /* Expansion register */
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#define MII_CTRL1000 0x09 /* 1000BASE-T control */
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#define MII_STAT1000 0x0a /* 1000BASE-T status */
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#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
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#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
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#define MII_ESTATUS 0x0f /* Extended Status */
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#define MII_DCOUNTER 0x12 /* Disconnect counter */
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#define MII_FCSCOUNTER 0x13 /* False carrier counter */
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#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
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#define MII_RERRCOUNTER 0x15 /* Receive error counter */
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#define MII_SREVISION 0x16 /* Silicon revision */
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#define MII_RESV1 0x17 /* Reserved... */
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#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
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#define MII_PHYADDR 0x19 /* PHY address */
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#define MII_RESV2 0x1a /* Reserved... */
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#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
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#define MII_NCONFIG 0x1c /* Network interface config */
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#define TIMEOUT_RESOLUTION 50
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#define PHY_CONNECT_TIMEOUT 5000
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#define USB_BULK_SEND_TIMEOUT 5000
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#define USB_BULK_RECV_TIMEOUT 5000
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#define R8152_WAIT_TIMEOUT 2000
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struct rx_desc {
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__le32 opts1;
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#define RD_CRC BIT(15)
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#define RX_LEN_MASK 0x7fff
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__le32 opts2;
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#define RD_UDP_CS BIT(23)
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#define RD_TCP_CS BIT(22)
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#define RD_IPV6_CS BIT(20)
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#define RD_IPV4_CS BIT(19)
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__le32 opts3;
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#define IPF BIT(23) /* IP checksum fail */
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#define UDPF BIT(22) /* UDP checksum fail */
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#define TCPF BIT(21) /* TCP checksum fail */
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#define RX_VLAN_TAG BIT(16)
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__le32 opts4;
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__le32 opts5;
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__le32 opts6;
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};
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struct tx_desc {
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__le32 opts1;
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#define TX_FS BIT(31) /* First segment of a packet */
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#define TX_LS BIT(30) /* Final segment of a packet */
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#define LGSEND BIT(29)
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#define GTSENDV4 BIT(28)
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#define GTSENDV6 BIT(27)
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#define GTTCPHO_SHIFT 18
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#define GTTCPHO_MAX 0x7fU
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#define TX_LEN_MAX 0x3ffffU
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__le32 opts2;
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#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
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#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
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#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
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#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
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#define MSS_SHIFT 17
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#define MSS_MAX 0x7ffU
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#define TCPHO_SHIFT 17
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#define TCPHO_MAX 0x7ffU
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#define TX_VLAN_TAG BIT(16)
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};
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enum rtl_version {
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RTL_VER_UNKNOWN = 0,
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RTL_VER_01,
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RTL_VER_02,
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RTL_VER_03,
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RTL_VER_04,
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RTL_VER_05,
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RTL_VER_06,
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RTL_VER_07,
|
RTL_VER_MAX
|
};
|
|
enum rtl_register_content {
|
_1000bps = 0x10,
|
_100bps = 0x08,
|
_10bps = 0x04,
|
LINK_STATUS = 0x02,
|
FULL_DUP = 0x01,
|
};
|
|
struct r8152 {
|
struct usb_device *udev;
|
struct usb_interface *intf;
|
bool supports_gmii;
|
|
struct rtl_ops {
|
void (*init)(struct r8152 *);
|
int (*enable)(struct r8152 *);
|
void (*disable)(struct r8152 *);
|
void (*up)(struct r8152 *);
|
void (*down)(struct r8152 *);
|
void (*unload)(struct r8152 *);
|
} rtl_ops;
|
|
u32 coalesce;
|
u16 ocp_base;
|
|
u8 version;
|
|
#ifdef CONFIG_DM_ETH
|
struct ueth_data ueth;
|
#endif
|
};
|
|
int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
|
u16 size, void *data, u16 type);
|
int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
|
void *data, u16 type);
|
|
int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
|
int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
|
u16 size, void *data);
|
|
int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
|
int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
|
u16 size, void *data);
|
|
u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index);
|
void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data);
|
|
u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index);
|
void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data);
|
|
u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index);
|
void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data);
|
|
u16 ocp_reg_read(struct r8152 *tp, u16 addr);
|
void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data);
|
|
void sram_write(struct r8152 *tp, u16 addr, u16 data);
|
|
int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
|
const u32 mask, bool set, unsigned int timeout);
|
|
void r8152b_firmware(struct r8152 *tp);
|
void r8153_firmware(struct r8152 *tp);
|
#endif
|
