/**
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* samsung_usb_phy.c - DesignWare USB3 (DWC3) PHY handling file
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*
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* Copyright (C) 2015 Samsung Electronics
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*
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* Author: Joonyoung Shim <jy0922.shim@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/arch/power.h>
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#include <asm/arch/xhci-exynos.h>
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void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
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{
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u32 reg;
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/* Reset USB 3.0 PHY */
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writel(0x0, &phy->phy_reg0);
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clrbits_le32(&phy->phy_param0,
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/* Select PHY CLK source */
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PHYPARAM0_REF_USE_PAD |
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/* Set Loss-of-Signal Detector sensitivity */
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PHYPARAM0_REF_LOSLEVEL_MASK);
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setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
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writel(0x0, &phy->phy_resume);
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/*
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* Setting the Frame length Adj value[6:1] to default 0x20
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* See xHCI 1.0 spec, 5.2.4
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*/
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setbits_le32(&phy->link_system,
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LINKSYSTEM_XHCI_VERSION_CONTROL |
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LINKSYSTEM_FLADJ(0x20));
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/* Set Tx De-Emphasis level */
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clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
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setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
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setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
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/* PHYTEST POWERDOWN Control */
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clrbits_le32(&phy->phy_test,
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PHYTEST_POWERDOWN_SSP |
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PHYTEST_POWERDOWN_HSP);
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/* UTMI Power Control */
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writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
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/* Use core clock from main PLL */
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reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
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/* Default 24Mhz crystal clock */
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PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
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PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
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PHYCLKRST_SSC_REFCLKSEL(0) |
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/* Force PortReset of PHY */
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PHYCLKRST_PORTRESET |
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/* Digital power supply in normal operating mode */
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PHYCLKRST_RETENABLEN |
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/* Enable ref clock for SS function */
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PHYCLKRST_REF_SSP_EN |
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/* Enable spread spectrum */
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PHYCLKRST_SSC_EN |
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/* Power down HS Bias and PLL blocks in suspend mode */
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PHYCLKRST_COMMONONN;
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writel(reg, &phy->phy_clk_rst);
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/* giving time to Phy clock to settle before resetting */
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udelay(10);
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reg &= ~PHYCLKRST_PORTRESET;
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writel(reg, &phy->phy_clk_rst);
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}
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