/*
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _QUARK_IOMAP_H_
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#define _QUARK_IOMAP_H_
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/* Memory Mapped IO bases */
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/* ESRAM */
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#define ESRAM_BASE_ADDRESS CONFIG_ESRAM_BASE
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#define ESRAM_BASE_SIZE ESRAM_SIZE
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/* PCI Configuration Space */
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#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
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#define MCFG_BASE_SIZE 0x10000000
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/* High Performance Event Timer */
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#define HPET_BASE_ADDRESS 0xfed00000
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#define HPET_BASE_SIZE 0x400
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/* Root Complex Base Address */
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#define RCBA_BASE_ADDRESS CONFIG_RCBA_BASE
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#define RCBA_BASE_SIZE 0x4000
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/* IO Port bases */
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#define ACPI_PM1_BASE_ADDRESS CONFIG_ACPI_PM1_BASE
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#define ACPI_PM1_BASE_SIZE 0x10
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#define ACPI_PBLK_BASE_ADDRESS CONFIG_ACPI_PBLK_BASE
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#define ACPI_PBLK_BASE_SIZE 0x10
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#define SPI_DMA_BASE_ADDRESS CONFIG_SPI_DMA_BASE
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#define SPI_DMA_BASE_SIZE 0x10
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#define GPIO_BASE_ADDRESS CONFIG_GPIO_BASE
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#define GPIO_BASE_SIZE 0x80
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#define ACPI_GPE0_BASE_ADDRESS CONFIG_ACPI_GPE0_BASE
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#define ACPI_GPE0_BASE_SIZE 0x40
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#define WDT_BASE_ADDRESS CONFIG_WDT_BASE
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#define WDT_BASE_SIZE 0x40
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#endif /* _QUARK_IOMAP_H_ */
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