/*
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* (C) Copyright 2016
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* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _STM32_GPT_H
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#define _STM32_GPT_H
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#include <asm/arch/stm32.h>
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struct gpt_regs {
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u32 cr1;
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u32 cr2;
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u32 smcr;
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u32 dier;
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u32 sr;
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u32 egr;
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u32 ccmr1;
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u32 ccmr2;
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u32 ccer;
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u32 cnt;
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u32 psc;
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u32 arr;
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u32 reserved;
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u32 ccr1;
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u32 ccr2;
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u32 ccr3;
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u32 ccr4;
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u32 reserved1;
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u32 dcr;
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u32 dmar;
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u32 tim2_5_or;
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};
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struct gpt_regs *const gpt1_regs_ptr =
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(struct gpt_regs *)TIM2_BASE;
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/* Timer control1 register */
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#define GPT_CR1_CEN BIT(0)
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#define GPT_MODE_AUTO_RELOAD BIT(7)
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/* Auto reload register for free running config */
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#define GPT_FREE_RUNNING 0xFFFFFFFF
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/* Timer, HZ specific defines */
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#define CONFIG_STM32_HZ 1000
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/* Timer Event Generation registers */
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#define TIM_EGR_UG BIT(0)
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#endif
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