/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __NV_TYPE_H__
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#define __NV_TYPE_H__
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#include <linux/fb.h>
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#include <linux/types.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <video/vga.h>
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#define NV_ARCH_04 0x04
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#define NV_ARCH_10 0x10
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#define NV_ARCH_20 0x20
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#define NV_ARCH_30 0x30
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#define NV_ARCH_40 0x40
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#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
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#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
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#define SetBF(mask,value) ((value) << (0?mask))
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#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
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#define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
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#define SetBit(n) (1<<(n))
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#define Set8Bits(value) ((value)&0xff)
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#define V_DBLSCAN 1
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typedef struct {
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int bitsPerPixel;
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int depth;
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int displayWidth;
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int weight;
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} NVFBLayout;
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#define NUM_SEQ_REGS 0x05
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#define NUM_CRT_REGS 0x41
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#define NUM_GRC_REGS 0x09
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#define NUM_ATC_REGS 0x15
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struct nvidia_par;
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struct nvidia_i2c_chan {
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struct nvidia_par *par;
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unsigned long ddc_base;
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struct i2c_adapter adapter;
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struct i2c_algo_bit_data algo;
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};
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typedef struct _riva_hw_state {
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u8 attr[NUM_ATC_REGS];
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u8 crtc[NUM_CRT_REGS];
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u8 gra[NUM_GRC_REGS];
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u8 seq[NUM_SEQ_REGS];
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u8 misc_output;
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u32 bpp;
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u32 width;
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u32 height;
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u32 interlace;
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u32 repaint0;
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u32 repaint1;
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u32 screen;
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u32 scale;
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u32 dither;
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u32 extra;
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u32 fifo;
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u32 pixel;
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u32 horiz;
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u32 arbitration0;
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u32 arbitration1;
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u32 pll;
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u32 pllB;
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u32 vpll;
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u32 vpll2;
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u32 vpllB;
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u32 vpll2B;
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u32 pllsel;
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u32 general;
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u32 crtcOwner;
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u32 head;
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u32 head2;
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u32 config;
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u32 cursorConfig;
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u32 cursor0;
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u32 cursor1;
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u32 cursor2;
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u32 timingH;
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u32 timingV;
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u32 displayV;
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u32 crtcSync;
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u32 control;
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} RIVA_HW_STATE;
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struct riva_regs {
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RIVA_HW_STATE ext;
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};
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struct nvidia_par {
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RIVA_HW_STATE SavedReg;
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RIVA_HW_STATE ModeReg;
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RIVA_HW_STATE initial_state;
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RIVA_HW_STATE *CurrentState;
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struct vgastate vgastate;
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u32 pseudo_palette[16];
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struct pci_dev *pci_dev;
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u32 Architecture;
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u32 CursorStart;
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int Chipset;
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unsigned long FbAddress;
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u8 __iomem *FbStart;
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u32 FbMapSize;
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u32 FbUsableSize;
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u32 ScratchBufferSize;
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u32 ScratchBufferStart;
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int FpScale;
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u32 MinVClockFreqKHz;
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u32 MaxVClockFreqKHz;
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u32 CrystalFreqKHz;
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u32 RamAmountKBytes;
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u32 IOBase;
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NVFBLayout CurrentLayout;
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int cursor_reset;
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int lockup;
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int videoKey;
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int FlatPanel;
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int FPDither;
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int Television;
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int CRTCnumber;
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int alphaCursor;
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int twoHeads;
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int twoStagePLL;
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int fpScaler;
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int fpWidth;
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int fpHeight;
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int PanelTweak;
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int paneltweak;
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int LVDS;
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int pm_state;
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int reverse_i2c;
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u32 crtcSync_read;
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u32 fpSyncs;
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u32 dmaPut;
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u32 dmaCurrent;
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u32 dmaFree;
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u32 dmaMax;
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u32 __iomem *dmaBase;
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u32 currentRop;
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int WaitVSyncPossible;
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int BlendingPossible;
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u32 paletteEnabled;
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u32 forceCRTC;
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u32 open_count;
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u8 DDCBase;
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int wc_cookie;
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struct nvidia_i2c_chan chan[3];
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volatile u32 __iomem *REGS;
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volatile u32 __iomem *PCRTC0;
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volatile u32 __iomem *PCRTC;
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volatile u32 __iomem *PRAMDAC0;
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volatile u32 __iomem *PFB;
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volatile u32 __iomem *PFIFO;
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volatile u32 __iomem *PGRAPH;
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volatile u32 __iomem *PEXTDEV;
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volatile u32 __iomem *PTIMER;
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volatile u32 __iomem *PMC;
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volatile u32 __iomem *PRAMIN;
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volatile u32 __iomem *FIFO;
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volatile u32 __iomem *CURSOR;
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volatile u8 __iomem *PCIO0;
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volatile u8 __iomem *PCIO;
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volatile u8 __iomem *PVIO;
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volatile u8 __iomem *PDIO0;
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volatile u8 __iomem *PDIO;
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volatile u32 __iomem *PRAMDAC;
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};
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#endif /* __NV_TYPE_H__ */
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