// SPDX-License-Identifier: GPL-2.0
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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******************************************************************************/
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#include "odm_precomp.h"
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/* This function is for inband noise test utility only */
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/* To obtain the inband noise level(dbm), do the following. */
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/* 1. disable DIG and Power Saving */
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/* 2. Set initial gain = 0x1a */
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/* 3. Stop updating idle time pwer report (for driver read) */
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/* - 0x80c[25] */
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#define Valid_Min -35
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#define Valid_Max 10
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#define ValidCnt 5
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static s16 odm_InbandNoise_Monitor_NSeries(
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PDM_ODM_T pDM_Odm,
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u8 bPauseDIG,
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u8 IGIValue,
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u32 max_time
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)
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{
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u32 tmp4b;
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u8 max_rf_path = 0, rf_path;
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u8 reg_c50, reg_c58, valid_done = 0;
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struct noise_level noise_data;
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u32 start = 0, func_start = 0, func_end = 0;
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func_start = jiffies;
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pDM_Odm->noise_level.noise_all = 0;
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if ((pDM_Odm->RFType == ODM_1T2R) || (pDM_Odm->RFType == ODM_2T2R))
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max_rf_path = 2;
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else
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max_rf_path = 1;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() ==>\n"));
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memset(&noise_data, 0, sizeof(struct noise_level));
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/* */
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/* Step 1. Disable DIG && Set initial gain. */
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/* */
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if (bPauseDIG)
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odm_PauseDIG(pDM_Odm, ODM_PAUSE_DIG, IGIValue);
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/* */
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/* Step 2. Disable all power save for read registers */
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/* */
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/* dcmd_DebugControlPowerSave(padapter, PSDisable); */
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/* */
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/* Step 3. Get noise power level */
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/* */
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start = jiffies;
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while (1) {
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/* Stop updating idle time pwer report (for driver read) */
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PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 1);
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/* Read Noise Floor Report */
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tmp4b = PHY_QueryBBReg(pDM_Odm->Adapter, 0x8f8, bMaskDWord);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b));
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/* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XAAGCCore1, bMaskByte0, TestInitialGain); */
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/* if (max_rf_path == 2) */
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/* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBAGCCore1, bMaskByte0, TestInitialGain); */
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/* update idle time pwer report per 5us */
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PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 0);
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noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b&0xff);
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noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b&0xff00)>>8);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n",
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noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B]));
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for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
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noise_data.sval[rf_path] = (s8)noise_data.value[rf_path];
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noise_data.sval[rf_path] /= 2;
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}
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("sval_a = %d, sval_b = %d\n",
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noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B]));
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/* mdelay(10); */
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/* msleep(10); */
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for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
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if ((noise_data.valid_cnt[rf_path] < ValidCnt) && (noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min)) {
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noise_data.valid_cnt[rf_path]++;
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noise_data.sum[rf_path] += noise_data.sval[rf_path];
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RF_Path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path]));
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", noise_data.sum[rf_path]));
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if (noise_data.valid_cnt[rf_path] == ValidCnt) {
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valid_done++;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, RF_Path:%d , sum = %d\n", rf_path, noise_data.sum[rf_path]));
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}
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}
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}
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/* printk("####### valid_done:%d #############\n", valid_done); */
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if ((valid_done == max_rf_path) || (jiffies_to_msecs(jiffies - start) > max_time)) {
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for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
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/* printk("%s PATH_%d - sum = %d, valid_cnt = %d\n", __func__, rf_path, noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]); */
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if (noise_data.valid_cnt[rf_path])
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noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path];
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else
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noise_data.sum[rf_path] = 0;
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}
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break;
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}
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}
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reg_c50 = (s32)PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XAAGCCore1, bMaskByte0);
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reg_c50 &= ~BIT7;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", rOFDM0_XAAGCCore1, reg_c50, reg_c50));
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pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = -110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A];
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pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A];
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if (max_rf_path == 2) {
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reg_c58 = (s32)PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBAGCCore1, bMaskByte0);
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reg_c58 &= ~BIT7;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", rOFDM0_XBAGCCore1, reg_c58, reg_c58));
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pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = -110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B];
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pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B];
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}
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pDM_Odm->noise_level.noise_all /= max_rf_path;
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ODM_RT_TRACE(
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pDM_Odm,
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ODM_COMP_COMMON,
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ODM_DBG_LOUD,
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(
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"noise_a = %d, noise_b = %d\n",
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pDM_Odm->noise_level.noise[ODM_RF_PATH_A],
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pDM_Odm->noise_level.noise[ODM_RF_PATH_B]
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)
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);
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/* */
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/* Step 4. Recover the Dig */
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/* */
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if (bPauseDIG)
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odm_PauseDIG(pDM_Odm, ODM_RESUME_DIG, IGIValue);
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func_end = jiffies_to_msecs(jiffies - func_start);
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/* printk("%s noise_a = %d, noise_b = %d noise_all:%d (%d ms)\n", __func__, */
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/* pDM_Odm->noise_level.noise[ODM_RF_PATH_A], */
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/* pDM_Odm->noise_level.noise[ODM_RF_PATH_B], */
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/* pDM_Odm->noise_level.noise_all, func_end); */
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n"));
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return pDM_Odm->noise_level.noise_all;
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}
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s16 ODM_InbandNoise_Monitor(void *pDM_VOID, u8 bPauseDIG, u8 IGIValue, u32 max_time)
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{
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return odm_InbandNoise_Monitor_NSeries(pDM_VOID, bPauseDIG, IGIValue, max_time);
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}
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