/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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******************************************************************************/
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#ifndef __HALHWOUTSRC_H__
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#define __HALHWOUTSRC_H__
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/*--------------------------Define -------------------------------------------*/
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/* define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0) */
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#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
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sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u32)))
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#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
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sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u32)))
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#define AGC_DIFF_CONFIG(ic, band)\
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do {\
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if (pDM_Odm->bIsMPChip)\
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AGC_DIFF_CONFIG_MP(ic, band);\
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else\
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AGC_DIFF_CONFIG_TC(ic, band);\
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} while (0)
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/* */
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/* structure and define */
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/* */
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typedef struct _Phy_Rx_AGC_Info {
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#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
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u8 gain:7, trsw:1;
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#else
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u8 trsw:1, gain:7;
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#endif
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} PHY_RX_AGC_INFO_T, *pPHY_RX_AGC_INFO_T;
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typedef struct _Phy_Status_Rpt_8192cd {
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PHY_RX_AGC_INFO_T path_agc[2];
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u8 ch_corr[2];
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u8 cck_sig_qual_ofdm_pwdb_all;
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u8 cck_agc_rpt_ofdm_cfosho_a;
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u8 cck_rpt_b_ofdm_cfosho_b;
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u8 rsvd_1;/* ch_corr_msb; */
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u8 noise_power_db_msb;
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s8 path_cfotail[2];
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u8 pcts_mask[2];
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s8 stream_rxevm[2];
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u8 path_rxsnr[2];
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u8 noise_power_db_lsb;
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u8 rsvd_2[3];
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u8 stream_csi[2];
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u8 stream_target_csi[2];
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s8 sig_evm;
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u8 rsvd_3;
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#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
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u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
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u8 sgi_en:1;
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u8 rxsc:2;
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u8 idle_long:1;
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u8 r_ant_train_en:1;
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u8 ant_sel_b:1;
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u8 ant_sel:1;
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#else /* _BIG_ENDIAN_ */
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u8 ant_sel:1;
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u8 ant_sel_b:1;
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u8 r_ant_train_en:1;
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u8 idle_long:1;
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u8 rxsc:2;
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u8 sgi_en:1;
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u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
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#endif
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} PHY_STATUS_RPT_8192CD_T, *PPHY_STATUS_RPT_8192CD_T;
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typedef struct _Phy_Status_Rpt_8812 {
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/* 2012.05.24 LukeLee: This structure should take big/little endian in consideration later..... */
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/* DWORD 0 */
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u8 gain_trsw[2];
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#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
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u16 chl_num:10;
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u16 sub_chnl:4;
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u16 r_RFMOD:2;
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#else /* _BIG_ENDIAN_ */
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u16 r_RFMOD:2;
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u16 sub_chnl:4;
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u16 chl_num:10;
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#endif
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/* DWORD 1 */
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u8 pwdb_all;
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u8 cfosho[4]; /* DW 1 byte 1 DW 2 byte 0 */
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/* DWORD 2 */
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s8 cfotail[4]; /* DW 2 byte 1 DW 3 byte 0 */
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/* DWORD 3 */
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s8 rxevm[2]; /* DW 3 byte 1 DW 3 byte 2 */
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s8 rxsnr[2]; /* DW 3 byte 3 DW 4 byte 0 */
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/* DWORD 4 */
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u8 PCTS_MSK_RPT[2];
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u8 pdsnr[2]; /* DW 4 byte 3 DW 5 Byte 0 */
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/* DWORD 5 */
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u8 csi_current[2];
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u8 rx_gain_c;
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/* DWORD 6 */
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u8 rx_gain_d;
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s8 sigevm;
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u8 resvd_0;
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u8 antidx_anta:3;
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u8 antidx_antb:3;
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u8 resvd_1:2;
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} PHY_STATUS_RPT_8812_T, *PPHY_STATUS_RPT_8812_T;
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void ODM_PhyStatusQuery(
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PDM_ODM_T pDM_Odm,
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struct odm_phy_info *pPhyInfo,
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u8 *pPhyStatus,
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struct odm_packet_info *pPktinfo
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);
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HAL_STATUS ODM_ConfigRFWithTxPwrTrackHeaderFile(PDM_ODM_T pDM_Odm);
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HAL_STATUS ODM_ConfigRFWithHeaderFile(
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PDM_ODM_T pDM_Odm,
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ODM_RF_Config_Type ConfigType,
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ODM_RF_RADIO_PATH_E eRFPath
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);
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HAL_STATUS ODM_ConfigBBWithHeaderFile(
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PDM_ODM_T pDM_Odm, ODM_BB_Config_Type ConfigType
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);
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HAL_STATUS ODM_ConfigFWWithHeaderFile(
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PDM_ODM_T pDM_Odm,
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ODM_FW_Config_Type ConfigType,
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u8 *pFirmware,
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u32 *pSize
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);
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s32 odm_SignalScaleMapping(PDM_ODM_T pDM_Odm, s32 CurrSig);
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#endif
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