/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
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*
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* Contact Information: wlanfae <wlanfae@realtek.com>
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*/
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#ifndef _R819XU_PHY_H
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#define _R819XU_PHY_H
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#define MAX_DOZE_WAITING_TIMES_9x 64
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#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE
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#define MACPHY_ArrayLength MACPHY_ArrayLengthPciE
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#define RadioA_ArrayLength RadioA_ArrayLengthPciE
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#define RadioB_ArrayLength RadioB_ArrayLengthPciE
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#define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE
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#define RadioC_ArrayLength RadioC_ArrayLengthPciE
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#define RadioD_ArrayLength RadioD_ArrayLengthPciE
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#define PHY_REGArrayLength PHY_REGArrayLengthPciE
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#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE
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#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
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#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
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#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
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#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
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#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array
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#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array
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#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
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#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
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#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
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extern u32 rtl819XAGCTAB_Array[];
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enum hw90_block {
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HW90_BLOCK_MAC = 0,
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HW90_BLOCK_PHY0 = 1,
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HW90_BLOCK_PHY1 = 2,
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HW90_BLOCK_RF = 3,
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HW90_BLOCK_MAXIMUM = 4,
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};
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enum rf90_radio_path {
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RF90_PATH_A = 0,
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RF90_PATH_B = 1,
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RF90_PATH_C = 2,
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RF90_PATH_D = 3,
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RF90_PATH_MAX
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};
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#define bMaskByte0 0xff
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#define bMaskByte1 0xff00
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#define bMaskByte2 0xff0000
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#define bMaskByte3 0xff000000
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#define bMaskHWord 0xffff0000
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#define bMaskLWord 0x0000ffff
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#define bMaskDWord 0xffffffff
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u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath);
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void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr,
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u32 dwBitMask, u32 dwData);
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u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask);
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void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
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u32 RegAddr, u32 BitMask, u32 Data);
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u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
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u32 RegAddr, u32 BitMask);
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void rtl92e_config_mac(struct net_device *dev);
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bool rtl92e_check_bb_and_rf(struct net_device *dev,
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enum hw90_block CheckBlock,
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enum rf90_radio_path eRFPath);
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bool rtl92e_config_bb(struct net_device *dev);
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void rtl92e_get_tx_power(struct net_device *dev);
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void rtl92e_set_tx_power(struct net_device *dev, u8 channel);
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bool rtl92e_config_phy(struct net_device *dev);
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u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath);
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u8 rtl92e_set_channel(struct net_device *dev, u8 channel);
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void rtl92e_set_bw_mode(struct net_device *dev,
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enum ht_channel_width Bandwidth,
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enum ht_extchnl_offset Offset);
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void rtl92e_init_gain(struct net_device *dev, u8 Operation);
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void rtl92e_set_rf_off(struct net_device *dev);
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bool rtl92e_set_rf_power_state(struct net_device *dev,
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enum rt_rf_power_state eRFPowerState);
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#define PHY_SetRFPowerState rtl92e_set_rf_power_state
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void rtl92e_scan_op_backup(struct net_device *dev, u8 Operation);
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#endif
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