// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
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*
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* Contact Information: wlanfae <wlanfae@realtek.com>
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*/
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#include "rtl_core.h"
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#include "r8192E_phyreg.h"
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#include "r8192E_phy.h"
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#include "r8190P_rtl8256.h"
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void rtl92e_set_bandwidth(struct net_device *dev,
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enum ht_channel_width Bandwidth)
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{
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u8 eRFPath;
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struct r8192_priv *priv = rtllib_priv(dev);
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if (priv->card_8192_version != VERSION_8190_BD &&
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priv->card_8192_version != VERSION_8190_BE) {
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netdev_warn(dev, "%s(): Unknown HW version.\n", __func__);
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return;
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}
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for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) {
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if (!rtl92e_is_legal_rf_path(dev, eRFPath))
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continue;
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switch (Bandwidth) {
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case HT_CHANNEL_WIDTH_20:
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rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
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0x0b, bMask12Bits, 0x100);
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rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
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0x2c, bMask12Bits, 0x3d7);
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rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
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0x0e, bMask12Bits, 0x021);
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break;
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case HT_CHANNEL_WIDTH_20_40:
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rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
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0x0b, bMask12Bits, 0x300);
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rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
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0x2c, bMask12Bits, 0x3ff);
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rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
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0x0e, bMask12Bits, 0x0e1);
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break;
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default:
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netdev_err(dev, "%s(): Unknown bandwidth: %#X\n",
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__func__, Bandwidth);
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break;
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}
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}
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}
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bool rtl92e_config_rf(struct net_device *dev)
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{
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u32 u4RegValue = 0;
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u8 eRFPath;
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bool rtStatus = true;
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struct bb_reg_definition *pPhyReg;
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struct r8192_priv *priv = rtllib_priv(dev);
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u32 RegOffSetToBeCheck = 0x3;
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u32 RegValueToBeCheck = 0x7f1;
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u32 RF3_Final_Value = 0;
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u8 ConstRetryTimes = 5, RetryTimes = 5;
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u8 ret = 0;
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priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
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for (eRFPath = (enum rf90_radio_path)RF90_PATH_A;
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eRFPath < priv->NumTotalRFPath; eRFPath++) {
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if (!rtl92e_is_legal_rf_path(dev, eRFPath))
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continue;
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pPhyReg = &priv->PHYRegDef[eRFPath];
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switch (eRFPath) {
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case RF90_PATH_A:
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case RF90_PATH_C:
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u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs,
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bRFSI_RFENV);
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break;
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case RF90_PATH_B:
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case RF90_PATH_D:
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u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs,
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bRFSI_RFENV<<16);
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break;
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}
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rtl92e_set_bb_reg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
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rtl92e_set_bb_reg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
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rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
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b3WireAddressLength, 0x0);
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rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
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b3WireDataLength, 0x0);
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rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 0x0,
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bMask12Bits, 0xbf);
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rtStatus = rtl92e_check_bb_and_rf(dev, HW90_BLOCK_RF,
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(enum rf90_radio_path)eRFPath);
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if (!rtStatus) {
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netdev_err(dev, "%s(): Failed to check RF Path %d.\n",
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__func__, eRFPath);
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goto fail;
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}
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RetryTimes = ConstRetryTimes;
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RF3_Final_Value = 0;
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while (RF3_Final_Value != RegValueToBeCheck &&
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RetryTimes != 0) {
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ret = rtl92e_config_rf_path(dev,
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(enum rf90_radio_path)eRFPath);
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RF3_Final_Value = rtl92e_get_rf_reg(dev,
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(enum rf90_radio_path)eRFPath,
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RegOffSetToBeCheck,
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bMask12Bits);
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RT_TRACE(COMP_RF,
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"RF %d %d register final value: %x\n",
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eRFPath, RegOffSetToBeCheck,
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RF3_Final_Value);
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RetryTimes--;
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}
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switch (eRFPath) {
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case RF90_PATH_A:
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case RF90_PATH_C:
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rtl92e_set_bb_reg(dev, pPhyReg->rfintfs, bRFSI_RFENV,
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u4RegValue);
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break;
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case RF90_PATH_B:
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case RF90_PATH_D:
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rtl92e_set_bb_reg(dev, pPhyReg->rfintfs,
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bRFSI_RFENV<<16, u4RegValue);
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break;
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}
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if (ret) {
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netdev_err(dev,
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"%s(): Failed to initialize RF Path %d.\n",
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__func__, eRFPath);
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goto fail;
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}
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}
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RT_TRACE(COMP_PHY, "PHY Initialization Success\n");
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return true;
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fail:
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return false;
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}
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void rtl92e_set_cck_tx_power(struct net_device *dev, u8 powerlevel)
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{
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u32 TxAGC = 0;
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struct r8192_priv *priv = rtllib_priv(dev);
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TxAGC = powerlevel;
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if (priv->bDynamicTxLowPower) {
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if (priv->CustomerID == RT_CID_819x_Netcore)
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TxAGC = 0x22;
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else
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TxAGC += priv->CckPwEnl;
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}
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if (TxAGC > 0x24)
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TxAGC = 0x24;
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rtl92e_set_bb_reg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
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}
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void rtl92e_set_ofdm_tx_power(struct net_device *dev, u8 powerlevel)
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{
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struct r8192_priv *priv = rtllib_priv(dev);
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u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
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u8 index = 0;
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u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
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u8 byte0, byte1, byte2, byte3;
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powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff;
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powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
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(powerBase0 << 8) | powerBase0;
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powerBase1 = powerlevel;
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powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) |
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(powerBase1 << 8) | powerBase1;
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for (index = 0; index < 6; index++) {
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writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] +
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((index < 2) ? powerBase0 : powerBase1));
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byte0 = (u8)(writeVal & 0x7f);
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byte1 = (u8)((writeVal & 0x7f00)>>8);
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byte2 = (u8)((writeVal & 0x7f0000)>>16);
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byte3 = (u8)((writeVal & 0x7f000000)>>24);
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if (byte0 > 0x24)
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byte0 = 0x24;
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if (byte1 > 0x24)
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byte1 = 0x24;
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if (byte2 > 0x24)
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byte2 = 0x24;
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if (byte3 > 0x24)
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byte3 = 0x24;
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if (index == 3) {
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writeVal_tmp = (byte3 << 24) | (byte2 << 16) |
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(byte1 << 8) | byte0;
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priv->Pwr_Track = writeVal_tmp;
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}
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if (priv->bDynamicTxHighPower)
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writeVal = 0x03030303;
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else
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writeVal = (byte3 << 24) | (byte2 << 16) |
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(byte1 << 8) | byte0;
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rtl92e_set_bb_reg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
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}
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}
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