/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
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*
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* Contact Information: wlanfae <wlanfae@realtek.com>
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*/
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#ifndef R8190P_DEF_H
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#define R8190P_DEF_H
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#include <linux/types.h>
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#define MAX_SILENT_RESET_RX_SLOT_NUM 10
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#define RX_MPDU_QUEUE 0
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enum rtl819x_loopback {
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RTL819X_NO_LOOPBACK = 0,
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RTL819X_MAC_LOOPBACK = 1,
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RTL819X_DMA_LOOPBACK = 2,
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RTL819X_CCK_LOOPBACK = 3,
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};
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#define DESC90_RATE1M 0x00
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#define DESC90_RATE2M 0x01
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#define DESC90_RATE5_5M 0x02
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#define DESC90_RATE11M 0x03
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#define DESC90_RATE6M 0x04
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#define DESC90_RATE9M 0x05
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#define DESC90_RATE12M 0x06
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#define DESC90_RATE18M 0x07
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#define DESC90_RATE24M 0x08
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#define DESC90_RATE36M 0x09
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#define DESC90_RATE48M 0x0a
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#define DESC90_RATE54M 0x0b
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#define DESC90_RATEMCS0 0x00
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#define DESC90_RATEMCS1 0x01
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#define DESC90_RATEMCS2 0x02
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#define DESC90_RATEMCS3 0x03
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#define DESC90_RATEMCS4 0x04
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#define DESC90_RATEMCS5 0x05
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#define DESC90_RATEMCS6 0x06
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#define DESC90_RATEMCS7 0x07
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#define DESC90_RATEMCS8 0x08
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#define DESC90_RATEMCS9 0x09
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#define DESC90_RATEMCS10 0x0a
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#define DESC90_RATEMCS11 0x0b
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#define DESC90_RATEMCS12 0x0c
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#define DESC90_RATEMCS13 0x0d
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#define DESC90_RATEMCS14 0x0e
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#define DESC90_RATEMCS15 0x0f
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#define DESC90_RATEMCS32 0x20
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#define SHORT_SLOT_TIME 9
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#define NON_SHORT_SLOT_TIME 20
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#define RX_SMOOTH 20
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#define QSLT_BK 0x1
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#define QSLT_BE 0x0
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#define QSLT_VI 0x4
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#define QSLT_VO 0x6
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#define QSLT_BEACON 0x10
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#define QSLT_HIGH 0x11
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#define QSLT_MGNT 0x12
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#define QSLT_CMD 0x13
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#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007
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#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa
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#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024
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#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007
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#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10
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#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
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#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd
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#define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
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#define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
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#define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
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#define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
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#define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
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#define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
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#define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
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#define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
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#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
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#define HAL_PRIME_CHNL_OFFSET_LOWER 1
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#define HAL_PRIME_CHNL_OFFSET_UPPER 2
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enum version_8190_loopback {
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VERSION_8190_BD = 0x3,
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VERSION_8190_BE
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};
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#define IC_VersionCut_C 0x2
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#define IC_VersionCut_D 0x3
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#define IC_VersionCut_E 0x4
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enum rf_optype {
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RF_OP_By_SW_3wire = 0,
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RF_OP_By_FW,
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RF_OP_MAX
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};
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struct bb_reg_definition {
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u32 rfintfs;
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u32 rfintfi;
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u32 rfintfo;
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u32 rfintfe;
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u32 rf3wireOffset;
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u32 rfLSSI_Select;
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u32 rfTxGainStage;
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u32 rfHSSIPara1;
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u32 rfHSSIPara2;
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u32 rfSwitchControl;
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u32 rfAGCControl1;
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u32 rfAGCControl2;
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u32 rfRxIQImbalance;
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u32 rfRxAFE;
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u32 rfTxIQImbalance;
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u32 rfTxAFE;
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u32 rfLSSIReadBack;
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u32 rfLSSIReadBackPi;
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};
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struct tx_fwinfo_8190pci {
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u8 TxRate:7;
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u8 CtsEnable:1;
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u8 RtsRate:7;
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u8 RtsEnable:1;
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u8 TxHT:1;
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u8 Short:1;
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u8 TxBandwidth:1;
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u8 TxSubCarrier:2;
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u8 STBC:2;
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u8 AllowAggregation:1;
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u8 RtsHT:1;
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u8 RtsShort:1;
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u8 RtsBandwidth:1;
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u8 RtsSubcarrier:2;
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u8 RtsSTBC:2;
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u8 EnableCPUDur:1;
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u32 RxMF:2;
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u32 RxAMD:3;
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u32 TxPerPktInfoFeedback:1;
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u32 Reserved1:2;
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u32 TxAGCOffset:4;
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u32 TxAGCSign:1;
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u32 RAW_TXD:1;
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u32 Retry_Limit:4;
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u32 Reserved2:1;
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u32 PacketID:13;
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};
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struct log_int_8190 {
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u32 nIMR_COMDOK;
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u32 nIMR_MGNTDOK;
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u32 nIMR_HIGH;
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u32 nIMR_VODOK;
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u32 nIMR_VIDOK;
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u32 nIMR_BEDOK;
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u32 nIMR_BKDOK;
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u32 nIMR_ROK;
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u32 nIMR_RCOK;
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u32 nIMR_TBDOK;
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u32 nIMR_BDOK;
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u32 nIMR_RXFOVW;
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};
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struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
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u8 reserved:4;
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u8 rxsc:2;
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u8 sgi_en:1;
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u8 ex_intf_flag:1;
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};
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struct phy_sts_ofdm_819xpci {
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u8 trsw_gain_X[4];
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u8 pwdb_all;
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u8 cfosho_X[4];
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u8 cfotail_X[4];
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u8 rxevm_X[2];
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u8 rxsnr_X[4];
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u8 pdsnr_X[2];
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u8 csi_current_X[2];
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u8 csi_target_X[2];
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u8 sigevm;
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u8 max_ex_pwr;
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u8 sgi_en;
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u8 rxsc_sgien_exflg;
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};
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struct phy_sts_cck_819xpci {
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u8 adc_pwdb_X[4];
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u8 sq_rpt;
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u8 cck_agc_rpt;
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};
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#define PHY_RSSI_SLID_WIN_MAX 100
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#define PHY_Beacon_RSSI_SLID_WIN_MAX 10
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struct tx_desc {
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u16 PktSize;
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u8 Offset;
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u8 Reserved1:3;
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u8 CmdInit:1;
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u8 LastSeg:1;
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u8 FirstSeg:1;
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u8 LINIP:1;
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u8 OWN:1;
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u8 TxFWInfoSize;
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u8 RATid:3;
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u8 DISFB:1;
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u8 USERATE:1;
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u8 MOREFRAG:1;
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u8 NoEnc:1;
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u8 PIFS:1;
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u8 QueueSelect:5;
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u8 NoACM:1;
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u8 Resv:2;
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u8 SecCAMID:5;
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u8 SecDescAssign:1;
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u8 SecType:2;
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u16 TxBufferSize;
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u8 PktId:7;
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u8 Resv1:1;
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u8 Reserved2;
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u32 TxBuffAddr;
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u32 NextDescAddress;
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u32 Reserved5;
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u32 Reserved6;
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u32 Reserved7;
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};
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struct tx_desc_cmd {
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u16 PktSize;
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u8 Reserved1;
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u8 CmdType:3;
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u8 CmdInit:1;
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u8 LastSeg:1;
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u8 FirstSeg:1;
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u8 LINIP:1;
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u8 OWN:1;
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u16 ElementReport;
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u16 Reserved2;
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u16 TxBufferSize;
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u16 Reserved3;
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u32 TxBuffAddr;
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u32 NextDescAddress;
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u32 Reserved4;
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u32 Reserved5;
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u32 Reserved6;
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};
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struct rx_desc {
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u16 Length:14;
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u16 CRC32:1;
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u16 ICV:1;
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u8 RxDrvInfoSize;
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u8 Shift:2;
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u8 PHYStatus:1;
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u8 SWDec:1;
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u8 LastSeg:1;
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u8 FirstSeg:1;
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u8 EOR:1;
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u8 OWN:1;
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u32 Reserved2;
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u32 Reserved3;
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u32 BufferAddress;
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};
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struct rx_fwinfo {
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u16 Reserved1:12;
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u16 PartAggr:1;
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u16 FirstAGGR:1;
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u16 Reserved2:2;
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u8 RxRate:7;
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u8 RxHT:1;
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u8 BW:1;
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u8 SPLCP:1;
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u8 Reserved3:2;
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u8 PAM:1;
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u8 Mcast:1;
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u8 Bcast:1;
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u8 Reserved4:1;
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u32 TSFL;
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};
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#endif
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